digital LPF for high sampling rate input data

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aobosong

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hello all.

I am trying to understand how the Zurich lock in amplifier HF2LI LPF is implemented. The input signal is sampled at 210MSps but somehow the filter output bandwidth is really low.

I am interested in implementing something similar on a FPGA so any help is appreciated.

The spec on the website:
filter time constant 1 µs - 500 s
filter bandwidth 80 µHz - 220 kHz
filter slope 6, 12, 18, 24, 30, 36, 42, 48 dB/Oct

Could it be 8 cascaded IIR filters?
 

It should be added that cascading first order filters is not the usual way to implement a higher order filter. But it might be appropriate in this case. I guess that it has been mainly chosen for simplicity of design.

I didn't see it mentioned in the user manual, but the extreme input sampling to cut-off frequency ratio would usually suggest a multi-rate (decimating) design.
 

The output sample rate seems to be limited by the output method (USB and DAC), so decimation definitely happened.
Do you think there are decimation stages between the filters or one final decimation stage at the end of the filter chain?
 

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