digital logic gate creation

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vasanth kumar

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hi there,

there are two logic inputs i1 and i2. when both are 0 the output should be 0. and when both are 1, the output should be 1. in other conditions like 0 1 and 1 0, the previous state should be the output(dont care conditions). please help me with formula.
 

Based on your description...

Code: 
i1 i2 o | o'
========+===
0  0  x | 0
0  1  0 | 0
0  1  1 | 1
1  0  0 | 0
1  0  1 | 1
1  1  x | 1

Which isn't a "gate" as it latches the output when the the inputs aren't the same.

Either provide a better description or preferably a truth table.
 

i1 i2 o/p
========
0 0 0
0 1 X
1 0 X
1 1 1

this is my requirement.

- - - Updated - - -

with "AND" gate, for the inputs 0 and 1, 1 and 0 output is 0. but i need the previous output as the present output for those inputs.
 

You want this

i1 i2 o/p
========
0 0 0
0 1 w
1 0 w
1 1 1

where w is the previous state

X means you don't care/indeterminate

in another words an XOR high output gives the previous state [whatever that was]
otherwise an AND output
 

Qn-1XYQN
0000
0010
0100
0111
1000
1011
1101
1111

As from above table Qn-1 is previous state & X, Y are your inputs & Qn is your required output then the boolean function you are looking for is something like
Code: 
Q[SUB]n[/SUB] = YQ[SUB]n-1[/SUB] + XQ[SUB]n-1[/SUB] + XY
 

i1 i2 o/p
========
0 0 0
0 1 X
1 0 X
1 1 1

this is my requirement.

- - - Updated - - -

with "AND" gate, for the inputs 0 and 1, 1 and 0 output is 0. but i need the previous output as the present output for those inputs.
Click to expand...
Apart from unclear or ambiguous phrasing, a logical design using a previous state is a sequential circuit and must have a clock and specify an active edge. So the description is still incomplete.
 

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