Nort
Newbie level 1
Hi all,
This is my first post here. I hope someone can help me with the issue I'm currently struggling with. Earlier this year I got a prototype chip manufactured in a 65nm CMOS process of one of the big foundries. This prototype is supposed to be supplied by a core voltage of 1.2V and an IO voltage of 2.5V. I give both voltages seperately with a Rigol power supply to the specific cells in the IO ring. There is a digital IO cell for an external clock supply but the chip also features an internal clock based on a ring oscillator circuit. For some experiments that we want to perform we need to measure the (instantaneous) power consumption of the core area of the chip. Now when I do that I see a huge amount of noise in the measurements when using the external clock supply. For every clock edge (rising and falling) I see a huge peak in the measurements of the core power. This noise, caused by the external clock, is orders of magnitude larger than the power consumption of the logic in the core area that I actually want to measure and thus significantly decreases the quality of my measurements. I was able to verify that this effect comes from the IO cell by repeating the same measurements with the internal clock, which is driving roughly the same clock tree. The effect is not present when using the internal clock.
Thus, my questions are: Why do my digital IO cells (in fact, it is not only the clock) draw such a significant current from the core power supply (since they are supposed to draw current from the IO power supply). Especially when they are receiving input and not driving any output signals. Is this normal behaviour? Is the level shifter in the IO cell drawing this current? Is there a way to avoid this effect in my measurements?
Further information:
- I performed the core power measurements by measuring the voltage drop over a shunt resistor in the Vdd path of the core power supply (i.e. IO power cons. should not be included)
- I tried to give a sine and a triangle wave to the external clock IO cell instead of a square one, but saw no changes.
I hope someone can help me.
Best regards,
Nort
This is my first post here. I hope someone can help me with the issue I'm currently struggling with. Earlier this year I got a prototype chip manufactured in a 65nm CMOS process of one of the big foundries. This prototype is supposed to be supplied by a core voltage of 1.2V and an IO voltage of 2.5V. I give both voltages seperately with a Rigol power supply to the specific cells in the IO ring. There is a digital IO cell for an external clock supply but the chip also features an internal clock based on a ring oscillator circuit. For some experiments that we want to perform we need to measure the (instantaneous) power consumption of the core area of the chip. Now when I do that I see a huge amount of noise in the measurements when using the external clock supply. For every clock edge (rising and falling) I see a huge peak in the measurements of the core power. This noise, caused by the external clock, is orders of magnitude larger than the power consumption of the logic in the core area that I actually want to measure and thus significantly decreases the quality of my measurements. I was able to verify that this effect comes from the IO cell by repeating the same measurements with the internal clock, which is driving roughly the same clock tree. The effect is not present when using the internal clock.
Thus, my questions are: Why do my digital IO cells (in fact, it is not only the clock) draw such a significant current from the core power supply (since they are supposed to draw current from the IO power supply). Especially when they are receiving input and not driving any output signals. Is this normal behaviour? Is the level shifter in the IO cell drawing this current? Is there a way to avoid this effect in my measurements?
Further information:
- I performed the core power measurements by measuring the voltage drop over a shunt resistor in the Vdd path of the core power supply (i.e. IO power cons. should not be included)
- I tried to give a sine and a triangle wave to the external clock IO cell instead of a square one, but saw no changes.
I hope someone can help me.
Best regards,
Nort
