digital filter help needed

• Sep 29, 2003

• #1

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sajeev_antony

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I need to inplement a 16 tap fir filter in an FPGA.
Can any one help me in this.

 

• Sep 29, 2003

• #2

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eternal_nan

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You have three basic choices:
1. Parallel (also known as unrolled) structure, this is the one that you will see in most DSP text-books, with every filter delay implemented as explicit registers and one result sample is available every clock cycle.
2. MAC (multiply-accumulate) based, this one computes one tap per cycle and stores intermediate result in an accumulator, it would take 16 cycles to produce one output sample.
3. DA (distributed arithmetic) based, this method is similar to (2), in the sense that it requires 16 cycles to produce a result and it needs an accumulator, but no multiplyers are needed since their functionality is implemented in a look-up table (LUT).

Google for the above for terms and you will find a wealth of implementations that are well documented.

 

• Sep 29, 2003

• #3

flatulent

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fourth way

If your taps are symmetrical, you can save one multiplication by adding the taps (that have the same weighting factor) together two at a time and then multiplying. This will save you about 8 multiplies total.

 

• Sep 30, 2003

• #4

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ch_wen

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The shortest way is choose what kind of your fir, and then calculate the coefficent by the FDATOOL which intergrated in Matlab, import them to any DSP tools for FPGA such as Xilinx SystemGenerator for DSP and build the system.

 

• Oct 9, 2003

• #5

Al Farouk

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Xilinx and Altera sites contains a lot of application dealing with FIR filter design

 

• Oct 14, 2003

• #6

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mcauleyj

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Heres a site for a tool that provides Digital Filter design packages that can produce synthesisable VHDL if thats any use:

www.tyder.com

AFAIK, he has a new version due out soon that includes FFT - his website is currently being overhauled.

Yep I do know the guy who wrote the package!

J

 

• Oct 15, 2003

• #7

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Vonn

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ONEOVERT that is founded in www.tyde.com is very good but it's not free
and the evaluation version doesn't support the synthesisable VHDL

 

• Nov 6, 2003

• #8

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fxiao

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what kind of fpga are you using? if it is xilinx, you can use their core generator. It very handy and flexible. I used it to implemented 255 tap, 14bit coefficient, 12 bit input fir filter.
If you want to save resource, you can use chips with embedded MAC. It's fun. Good luck

 

• Nov 10, 2003

• #9

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mmttbb

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oho!!255 tap ,14 bit coefficient , 12 bit input !!too complex!!
what kind of fpag are you using??

 

• Nov 10, 2003

• #10

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fxiao

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spartan II xc2s200

 

• Nov 11, 2003

• #11

H

hienpv

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i think there is a google example at Altera's website!

 

• Nov 11, 2003

• #12

H

hienpv

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i have an example!

 

• Jun 16, 2004

• #13

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weilijun

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You can find valuable examples from the following address:
http://www.altera.com/support/examples/stratix/exm-stratix.html