Digital FIlter design need help

hi all

i want to make a digital filter which have sampling frequency 10000 Hz and cutoff frequency is 100 Hz.

I implemented the filter in FDA tool it showing that minimum order of filter required is more than 150 in case of FIR(equiliriple) and i certainly dont wana use that beacuse it will eat my hardware resources lot.

when i go for IIR filter minimum order required is 14 but coefficient are so small(in term of 10 power -17) that i cant implement in FPGA.

So my problem is that sampling frequency is too high as compare to cutoff frequency.

which type of filter i should use which work well for very low cutoff frequency and use less resources of my FPGA.


thanks in advance

when i go for IIR filter minimum order required is 14 but coefficient are so small(in term of 10 power -17) that i cant implement in FPGA.

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The statement is meaningles without telling the filter specification. Most likely, the problem is an unrealistic specification.

which type of filter i should use which work well for very low cutoff frequency

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You already found out that the high IR order is caused by the fs/fc ratio. This problem can't be circumvented. An IIR filter for fs/fc = 100 is an everyday's design. A certain increase in filter coeficient and accumulator width is involved of course.

In some cases, a decimating multi-rate design might reduce the effort, provided you can accept a lower output sampling rate. It's particular helpful if you rely on an IR filter type.

FvM said:

The statement is meaningles without telling the filter specification. Most likely, the problem is an unrealistic specification.

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my filter specification on FDA tool

filter butter worth fs =10000 Fpass = 100 , Fstop =150 and Apass = 1db and Astop =80 db

FvM said:

You already found out that the high IR order is caused by the fs/fc ratio. This problem can't be circumvented. An IIR filter for fs/fc = 100 is an everyday's design. A certain increase in filter coeficient and accumulator width is involved of course.

Click to expand...

please can you elaborate more what you wana suggest ?

FvM said:

In some cases, a decimating multi-rate design might reduce the effort, provided you can accept a lower output sampling rate. It's particular helpful if you rely on an IR filter type.

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i cant change anything i just got the specification of filter some one else gonna use it in my department.

The specification results in a rather high order IIR filter, e.g. 7th order elliptic. You'll probably want to use a design tool to calculate it. I don't see extreme coefficient values however.

Hi Fvm

it was great help what u told me above

i designed the filter but its not giving proper output to me on system generator.


i attached my file below

if u just see it and suggest what went wrong it will be lot of help.

more over when ever i implemented IIr filter in system gen it having some issue but i implemented many FIR filter working.

thanks in advance
cheers

Can you adding another factor of formular ?

Ex. ROI

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Can you adding another factor of formular ?

Ex. ROI

@ phongphanp thanks for reply i didnt get u properly what u wana ask ?

i didnt try any thing else
i used FDA tool and get the SOS matrix which correspond to 2nd order IIr filter cascade them with gain to get the 7 order filter.

any suggestion what went wrong will be great help for me. my .mdi(system genrator file) is attached above.

Unfortunately your design can't be viewed without having the Xilinx system generator block sets installed.

I prefer to work with generic HDL signal processing and don't use this System Generator or DSP Builder stuff.

I think you dont need such a high sample rate for such a low cutoff. Just try to decimate, filter at lower rate (this reduces the order) then upsample back to 10K. The easy way. More complex one - to use a special decimation and interpolation filters cascaded (multi-rate as FvM said), they dont need high orders but for your LPF the order will drop significantly