Digital Error Correction in 1.5 Bit Pipeline ADC

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mischivis

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I understand that digital error correction for a pipeline ADC which is based on 1.5 bit per stage
is used in order to correct offsets from comparator, opamp, etc. My question is, how does
it actually correct this offset? What is the exact mechanism that allows you to be able
to tolerate a larger comparator offset just because you have digital correction. The way I
see it, the digitial correction is just a bunch of adders!
 

I bet you wanted to post this in another section.

If you have bits then you can control switches, and the
switch can do whatever kind of circuit value / topology
modification you want (subject to its own performance
limits).

You could also cal-map the whole thing if you had enough
xxxROM memory.

What you do with the bits is up to your imagination. What
you think digital consists of, wants checking.
 

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