Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Digital Error Correction Function in 10 bit Pipeline ADC?

Status
Not open for further replies.

pnanda65675

Member level 2
Member level 2
Joined
May 24, 2004
Messages
45
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
433
Could somebody explain me cleary how does this Digital error correction blks functioning ? Is tat it'll correct the gain & linearity errors in individual DAC n amplifiers ? Ur ans is very much welcome..thanx
 

Re: Digital Error Correction Function in 10 bit Pipeline ADC

Dear pnanda65675,

Digital error correction is mainly used to correct the comparator offset in pipelineADC, for example, for 8+1 stage (8 1.5b/stage stages + 1 2bit/stage) pipelineADC, there will be 18 digital code (8*2+2) output, through digital error correction these 18 digital code will be transfered to 10bit final code needed. A simple digital error correction includes several ripple adders.

As for up to 10-bit pipelineADC, digital error correction can't meet the request,
digital calibration (digital or analog) will be adopted. A digital calibration may include some ram, state machine and etc., a analog calibration may be realized through several capacitors, switchs and etc.

You can refer to IEEE papers for more detailed information.:D

Bg,
 

Message is unavailable.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top