liusupeng
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Hi All,
I am working on digital PLL which include VCO, frequency divider, TDC, digital filter. I want to simulate the digital PLL in cadence. I have the transistor level implementation of all blocks including digital filter. If i include digital filter in the simulation using transistor level implementation, it take long time. Is there a way to include the digital filter as a gate or register level netlist instead of transistor level implementation in the simulation?
I am working on digital PLL which include VCO, frequency divider, TDC, digital filter. I want to simulate the digital PLL in cadence. I have the transistor level implementation of all blocks including digital filter. If i include digital filter in the simulation using transistor level implementation, it take long time. Is there a way to include the digital filter as a gate or register level netlist instead of transistor level implementation in the simulation?