Dificulty in understand STIL file generated by TetraMax

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I have small sequential circuit with two primary inputs(line1,line2). I want to generate test vectors for critical path. So I used DFT compiler to insert and stich scan chain and Primetime to get critical path. spf and synthesized verilog ouput files from DFT compiler and timing report from PT is used in TetraMax to generate following STIL file.
I have some questions regarding it.
1. why my clk,reset,test_si and test_se are in _pi? shold not just line1 and line2 are PI
2. is the sequence of test_si=10011 corresponds scan cells respectievely like b01.outp_reg.SI"=1, "b01.overflw_reg.SI"=0, "b01.\stato_reg[0] .SI"=0 !
"b01.\stato_reg[1] .SI"=1, "b01.\stato_reg[2] .SI" !=1 ;

3. If I want to observe the the transitions on critical path as indicated in PT in functional mode, should I keep my FFs in test_si(10011) state and then apply 00 on PIs for launch and capture clock ?

Thanks.

Code C - [expand]
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Signals {
   "line1" In; "line2" In; "reset" In; "clock" In; "test_si" In { ScanIn; } "test_se" In;
   "outp" Out; "overflw" Out; "test_so" Out { ScanOut; }
}
 
SignalGroups {
   "_pi" = '"clock" + "line1" + "line2" + "reset" + "test_si" + "test_se"'; // #signals=6
   "_in" = '"line1" + "line2" + "reset" + "clock" + "test_si" + "test_se"'; // #signals=6
   "all_inputs" = '"clock" + "line1" + "line2" + "reset" + "test_si" + "test_se"';
   // #signals=6
   "_po" = '"outp" + "overflw" + "test_so"'; // #signals=3
   "_si" = '"test_si"' { ScanIn; } // #signals=1
   "all_outputs" = '"outp" + "overflw" + "test_so"'; // #signals=3
   "all_ports" = '"all_inputs" + "all_outputs"'; // #signals=9
   "_clk" = '"clock" + "reset"'; // #signals=2
   "_so" = '"test_so"' { ScanOut; } // #signals=1
   "_out" = '"outp" + "overflw" + "test_so"'; // #signals=3
}
Timing {
   WaveformTable "_allclock_launch_capture_WFT_" {
      Period '100ns';
      Waveforms {
         "all_inputs" { 0 { '0ns' D; } }
         "all_inputs" { 1 { '0ns' U; } }
         "all_inputs" { Z { '0ns' Z; } }
         "all_inputs" { N { '0ns' N; } }
         "all_outputs" { X { '0ns' X; '40ns' X; } }
         "all_outputs" { H { '0ns' X; '40ns' H; } }
         "all_outputs" { L { '0ns' X; '40ns' L; } }
         "all_outputs" { T { '0ns' X; '40ns' T; } }
         "clock" { P { '0ns' D; '45ns' U; '55ns' D; } }
         "reset" { P { '0ns' D; '45ns' U; '55ns' D; } }
      }
   }
   WaveformTable "_multiclock_capture_WFT_" {
      Period '100ns';
      Waveforms {
         "all_inputs" { 0 { '0ns' D; } }
         "all_inputs" { 1 { '0ns' U; } }
         "all_inputs" { Z { '0ns' Z; } }
         "all_inputs" { N { '0ns' N; } }
         "all_outputs" { X { '0ns' X; '40ns' X; } }
         "all_outputs" { H { '0ns' X; '40ns' H; } }
         "all_outputs" { L { '0ns' X; '40ns' L; } }
         "all_outputs" { T { '0ns' X; '40ns' T; } }
         "clock" { P { '0ns' D; '45ns' U; '55ns' D; } }
         "reset" { P { '0ns' D; '45ns' U; '55ns' D; } }
      }
   }
   WaveformTable "_allclock_launch_WFT_" {
      Period '100ns';
      Waveforms {
         "all_inputs" { 0 { '0ns' D; } }
         "all_inputs" { 1 { '0ns' U; } }
         "all_inputs" { Z { '0ns' Z; } }
         "all_inputs" { N { '0ns' N; } }
         "all_outputs" { X { '0ns' X; '40ns' X; } }
         "all_outputs" { H { '0ns' X; '40ns' H; } }
         "all_outputs" { L { '0ns' X; '40ns' L; } }
         "all_outputs" { T { '0ns' X; '40ns' T; } }
         "clock" { P { '0ns' D; '45ns' U; '55ns' D; } }
         "reset" { P { '0ns' D; '45ns' U; '55ns' D; } }
      }
   }
   WaveformTable "_allclock_capture_WFT_" {
      Period '100ns';
      Waveforms {
         "all_inputs" { 0 { '0ns' D; } }
         "all_inputs" { 1 { '0ns' U; } }
         "all_inputs" { Z { '0ns' Z; } }
         "all_inputs" { N { '0ns' N; } }
         "all_outputs" { X { '0ns' X; '40ns' X; } }
         "all_outputs" { H { '0ns' X; '40ns' H; } }
         "all_outputs" { L { '0ns' X; '40ns' L; } }
         "all_outputs" { T { '0ns' X; '40ns' T; } }
         "clock" { P { '0ns' D; '45ns' U; '55ns' D; } }
         "reset" { P { '0ns' D; '45ns' U; '55ns' D; } }
      }
   }
   WaveformTable "_default_WFT_" {
      Period '100ns';
      Waveforms {
         "all_inputs" { 0 { '0ns' D; } }
         "all_inputs" { 1 { '0ns' U; } }
         "all_inputs" { Z { '0ns' Z; } }
         "all_inputs" { N { '0ns' N; } }
         "all_outputs" { X { '0ns' X; '40ns' X; } }
         "all_outputs" { H { '0ns' X; '40ns' H; } }
         "all_outputs" { L { '0ns' X; '40ns' L; } }
         "all_outputs" { T { '0ns' X; '40ns' T; } }
         "clock" { P { '0ns' D; '45ns' U; '55ns' D; } }
         "reset" { P { '0ns' D; '45ns' U; '55ns' D; } }
      }
   }
}
ScanStructures {
   ScanChain "1" {
      ScanLength 5;
      ScanIn "test_si";
      ScanOut "test_so";
      ScanInversion 0;
      ScanCells "b01.outp_reg.SI" "b01.overflw_reg.SI" "b01.\stato_reg[0] .SI" !
      "b01.\stato_reg[1] .SI" "b01.\stato_reg[2] .SI" ! ;
      ScanMasterClock "clock" ;
   }
}
PatternBurst "_burst_" {
   PatList { "_pattern_" {
   }
}}
PatternExec {
   PatternBurst "_burst_";
}
Procedures {
   "multiclock_capture" {
      W "_multiclock_capture_WFT_";
      C { "all_inputs"=0NN0NN; "all_outputs"=XXX; }
      V { "_pi"=######; "_po"=###; }
   }
   "allclock_capture" {
      W "_allclock_capture_WFT_";
      C { "all_inputs"=0NN0NN; "all_outputs"=XXX; }
      V { "_pi"=######; "_po"=###; }
   }
   "allclock_launch" {
      W "_allclock_launch_WFT_";
      C { "all_inputs"=0NN0NN; "all_outputs"=XXX; }
      V { "_pi"=######; "_po"=###; }
   }
   "allclock_launch_capture" {
      W "_allclock_launch_capture_WFT_";
      C { "all_inputs"=0NN0NN; "all_outputs"=XXX; }
      V { "_pi"=######; "_po"=###; }
   }
   "load_unload" {
      W "_default_WFT_";
      C { "all_inputs"=0NN0NN; "all_outputs"=XXX; }
      "Internal_scan_pre_shift": V { "test_se"=1; }
      Shift {          W "_default_WFT_";
         V { "_clk"=P0; "_si"=#; "_so"=#; }
      }
   }
}
MacroDefs {
   "test_setup" {
      W "_default_WFT_";
      C { "all_inputs"=NNNNNN; "all_outputs"=XXX; }
      V { "clock"=0; "reset"=0; }
      V { }
   }
}
Pattern "_pattern_" {
   W "_multiclock_capture_WFT_";
   "precondition all Signals": C { "_pi"=000000; "_po"=XXX; }
   Macro "test_setup";
   Ann {* full_sequential *}
   "pattern 0": Call "load_unload" { 
      "test_si"=10011; }
   Call "allclock_launch" { 
      "_pi"=P00001; }
   Call "allclock_capture" { 
      "_pi"=P00000; }
   W "_multiclock_capture_WFT_";
   Ann {* full_sequential *}
   "end 0 unload": Call "load_unload" { 
      "test_so"=HHLLH; }
}
 
Last edited by a moderator:

Hello,

First of all, If you want to cover critical path, you have to use Path Delay testing. Critical path are not covered by SA and Transition testing. Should you have generated Path delay patterns by providing the Critical paths?

1. PI means Primary Inputs. Scan IN, Clock, Scan enable are PIs. So it always come into _pi group.

2. Yes. Your understanding is correct.

Hope it helps.

Thanks & Regards,
Maulin
 

Hi Maulin,

Thanks for reply.
Yes, I have generated path delay test pattern by providing critical path from PT.
1. so for both line1 and line2 the test vector pattern is 00 at launch and capture clock?
2. But when I extracted the synthesized gate level netlist in cadence virtuoso and set the FFs as per test_si states and then apply 00 at line1 and line2 for two clock cycles I am not able to see same transitions on critical path as shown in PT. Do you have any idea what I am doing wrong?

Once again thanks for your efforts.



 

1. Yes. for launch and capture bot, line1 and line2 are 0.
2. Have you simulated this patterns?
Simulation pass or fail?
 

Yes, I did Hspice simulation of the circuit.But as I said I am not able to observe the same transitions. Is there any other way I can do simulation?

Thanks.

maulin sheth said:
1. Yes. for launch and capture bot, line1 and line2 are 0.
2. Have you simulated this patterns?
Simulation pass or fail?
Click to expand...
 

Do the gate level simulation using gate level simulator like vcs, nc-verilog. see that patterns are passing or failing.
 

maulin sheth said:
Do the gate level simulation using gate level simulator like vcs, nc-verilog. see that patterns are passing or failing.
Click to expand...

HI, I am trying to do logic simulation of STILDPV test bench file generated by tmax in VCS. I am using following command

vcs -R -I -full64 +acc+2 +libext+tsbvlib +define+tmax_vcde +vcs+vcdpluson +define_tmax_parallel -P stildpv_vcs.tab
libstildpv.a test_bench_stildpv.v netlist_design.v -v library.tsbvlib -l log_file_compilation.log -debug_pp ./simv -l
log_file_simulation.log

But it is not showing anything not even an error.
Please if you can help me on this.

Thanks.
 

Hi,
Please do the serial simulation instead of parallel.
I think, there is not any mismatch, right??
 

Hi Maulin,

Can you please elaborate procedure to generate test patterns that excites critical path for combinational circuits using tetramax ? I tried in sequential circuits by inserting scan chain and latter evaluating test patterns successfully in VCS. But for combinational circuit how I can do delay path testing ? Is there any procedure to insert virtual flops at input and output and that acts as scain flops to generate test pattern ?

Hope to hear from you soon.

Thanks.

maulin sheth said:
Hi,
Please do the serial simulation instead of parallel.
I think, there is not any mismatch, right??
Click to expand...
 

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