Diffusion area in MOS

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amitabh262002

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Hi all,
In MOS we draws one rectangle for Diffusion area,but source and drain is a seprate terminals.
So why they didnt get short with each other.
 

Hi,

You are talking from layout point of view but see it in 3D view (fabricated device view) and then you can understand that they are 2 different areas and not connected to each other. In layout we draw one piece of rectangle as diffusion and form the drains & sources for the devices. So don't go by the layout point of view but understand the fabrication point of view.

Paramjyothi
 

Thats because you also draw the polysilicon gate in between the source and the drain.
Please remember that what you see in your layout editor is the top view.
Hope the explanation helps!
 

if you get it's cross-section on the die you will definitely see that they are not shorted.there is an isolation between the drain and the source. Most layout books have that diagram. in layout,there is what we call algorithms. So that when we fabricate there will be no confusion. The machine knows it. Eventhough you draw it shorted using you're layout editor but it's not when fabricated. If you're familiar with dummy layers and reverse mask layers you will know what we mean.
 

see cross section, actually not shorted
 

there are logic operation done on layers in LVS and extraction, one of them is between Diffusion and poly, so whenever there is poly over diffusion the layout indicates MOS device, however during fabrication only the source and drain area are doped.
also usually in self aligned process the doping of the Diffusion is done after adding the poly, which means that the poly masks that area from being doped
 

Self-aligned technology is used. The poly-silicon(gate) is first fabricated and then use ion implantation to make source and drain. The middle area(channal) is blockded by the poly-silicon, so it won't short.

Regards,
Colin
 

Hi,

A layout is just a top-view. When u r drawing source and drain....u draw just a rectangle which appeared to be short...but the actual fabrication is not so simple. U first lay oxide layer followed by polysilicon gate over the wafer....and u etch out regions where u dont want poly.....followed by Source and Drain diffusion implants...and poly will act as a mask....and hence there will be no diffusion beneath poly.....so where is short...?

regards,
anup...
 

since gate is fabricated before fabricating diffusion regions, and the gate material acts as mask while fabricting the diffusion areas.
Please see the 3rd view in any of books, you will find in the 1st or 2nd chapter itself.
 

Hi,

colin and the last guy are correct.

first the poly will be fabricated then with the rectangle mask

source and drain will be fabricated . This time the poly will act as

a mask under poly there will not be any diffusion formed.

You can get the fabrication step in google there you will get more detail information.


Regards,

Analayout.
 

hey!!!
it is better to study fabrication steps in detail before to do layout.....even me also was having same kind of doubts until understand the fabrication steps...
 

hi
as colin said we use self-aligned process while fabricating th CMOS.in this, poly will be used as mask layer as it is deposited first then implantation for diffusions is carried out. The reason why poly is deposited first is, here we get exact length of the poly.but if we do it the other way like implanting the diffusions first and later depositing the poly we may not get the length of the poly.we caluculate the actual lentgh of the poly is the poly between S and D.so in the second case the mask may be moved and less chances of getting accurate length.
please see the attached diagram. i think its understtod and correct me if i am wrong.
 
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