Thank u very much sir but in our campus youtube is not allowed can u provide any different type to see in video.
Thank u in advance
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I need help in my thesis on Theoretical Analysis of Mos current mode logic(MCML) by using Cadence(Tool) Virtuoso .iam not getting results of simple inverter logic in MCML in both 180nm and 90nm tech with load as resitor and load as pmos in both cases .
And one more doubt plz in gpdk 180nm and gpdk 90nm technology how much vdd should give .In my thesis iam giving vdd=2.5v I think we can give upto 5v .what is the specification of vdd how it useful to design.if minimum gives what happend and if maxum?
i am attaching my schematic and waveforms please tell me where is error.
These schematics in Cadence Virtuoso 180nm technology:
Pmos as a load in MCML(Mos current mode logic)
Resistor as a load in MCML(Mos current mode logic)