Thanks FvM and Marce for detail explanation and helping hand on this matter.
It's good to have positive discussion on technical matter on the forum indeed.
For stripline case, 0.5mm approximately equates to 3.5ps.
Refer to the book "Signal Integrity and Printed Circuit Board Design" by Douglas Brooks, Chapter 14:
"The reason differential traces must be of equal length has almost nothing to do with signal timing. It has everything to do with the assumption that differential signals are equal and opposite and what happens when that assumption is violated .... Uncontrolled ground currents start flowing that at the very best are benign but at worst can generate serious common-mode EMI problems."
And according to "PCB Design for SI and EMC of Gb/s Differential Transmission Lines" by Keith Armstrong as posted by Marce, a differential skew as large as 80ps (part of factors of imbalance differential pair) worsens EMC and SI.
In view of these, one conclusion can be deducted that timing difference does not cause differential signalling to deteriorate, it's the imbalance that causes the differential signal to act like a worsened single-ended line, under high-speed condition, with widened return loop, causing emission eventually.
Length difference tolerance needs to be <1/10th of the signal's rise/fall time, so for my case, as stated by FvM, it is indeed been overcompensated. I doubted why our circuit designer proposed such harsh value to adhere to.
One thing I do not really understand in the notes from Keith Armstrong is that the serpentine routing causes "unbalanced trace pair", as in unbalanced coupling??
Say if the pin assignment hardly achieve balanced condition, what else can we do to balance the length of the pair besides using serpentine routing?
Is there a trade-off happens in this area, for eg. by consistently maintaining the coupling of trace pair and giving up of length mismatch??
Thanks!