Differential Pairs Length Matching

[nelsonys]

Dear All,

Kindly have a check on my ppt file for my observation and enquiries. I am having problems in theories and practical implementation.

Thanks a lot.

 

[marce]

Track impedances as well to think about, if they are matched diff pairs they would all be better as stripline, then the impedances will match better, and it would make the maths easier. If your system has high speed tools built in I would use them. With a mixture of microstrip and stripline you have to calculate the diff pair impedances (track width, distance to planes etc) for both occurances.
If you cant get them all on stripline layers, move more traces onto an inner layer so you have more room to match the lengths.
I would look at the lengths of the diff pairs, and post them if possible, because over that distance you shouldn't have a problem matching to 5mm. Find your longest diff pair and try to get all the other traces within 5mm of that length.

 

[andre_luis]

nelsonys


Despite you had provide specifications in distance and width, is usual to most communication standards inform requirements in impedance.
Depending on wich CAD are you using, it is possible to match desired impedance automactilly.

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[nelsonys]

I'm trying to layout differential pair for LAN. As you can find from the attachment, the pin assignment on the BGA for differential pairs made the spacing between differential pairs very small when a trace is routed in between them. So for differential traces suppose there should be a distance of 3W between adjacent pairs to avoid coupling, but obviously for this case, separation is insufficient and coupling might occur. The problem is this effect significant? And is there any rule of thumb (frequency, rise time, etc) that determines a boundary whether a coupling would be significant between differential pairs?

 

[andre_luis]

nelson

The document bellow can be used as a general guidance, despite had been privide for a specific IC manufacturer.
Note that minimun distance between pair tracks is half than you posted at .pps file ( 0.25 not 0.50 ).

ftp://ftp.efo.ru/pub/wiznet/RTL8201BL_layoutguide.pdf

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[nelsonys]

Thanks andre,

One more question:
Is it the circuit designer who decides to route a differential pair in tightly or loosely-coupled manner?
What is the criteria required to decide whether a differential pair should be routed in tightly-coupled manner?

 

[marce]

This is an interesting document, Lee W Ritchey quoted on page 2 has a free dwonload book thats also worth getting hold of "Right the First Time"
**broken link removed**

 

[FvM]

Thanks to marce for linking the interesting paper.

According to the original post, the involved signals are rather slow (a risetime of 4 ns is stated). I guess, it's 100 MBit ethernet? The strict intra-pair skew matching requirement of 0.5 mm seems arbitrary in this regard. You usually will have graduated spacing rules, depending on the parallel length, that should still allow a BGA fan-out.

The required adjacent pair spacing would depend more on the the substrate thickness than the trace width in case of screened internal layers, I think.

 

[nelsonys]

Thanks to marce too!

Yes it is somewhat arbitrary for setting strict rules for such case. Say for 50ps rise time, how do you design for diff pair? Tight-coupled or loose-coupled? how do you cope with skew matching issue (serpentine trace with minimum spacing possible?)? How do you solve for impedance discontinuity (diff. trace parted) imposed by obstacles in limited board space?

Thanks!

 

[marce]

I use Cadstar with the high speed router and signal integrity verify tools. What we do now is spend several days entering constraints and rules for all signal that are critical. Then when we interactively route we cant break the rules and have extra on screen info to guide us. I beleive in setting up the constraints beforehand, it makes the routing more intense, but when you have finished you are not going to get any nasty suprises. Without the tools it is a complete and utter nightmare, as you have no doubt gathered, trying to work out all the rules and how thing interact.
With my set up I can go from layer to layer and the track width will be altered accordingly to keep my required impedence, etc.
PCB design is changing, due to high speed/rise time etc, where we are having to become more disciplined in our rules, more constraint driven.

 

[andre_luis]

...How do you solve for impedance discontinuity (diff. trace parted) imposed by obstacles in limited board space?

nelsys


In some cases there are no precise answer.

For instance : I draw a PCB and routed traks for an IDE/SATA converter wich manufacturer guide specified a maximum of 100mm twisted pair at internal layer ( I had to route more than that distance - and at Top layer ).

In you case it is desirable to you check at IC driver you´re working to know about manufacturer specified constraints.
Also : You did not specified speed of ETH used at target application ( 10M / 100M / 1G ). It affects deeply further decisions concernig work around.

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[nelsonys]

Thanks Marce and Andre,

I'm routing 100M Ethernet only. By the way, for length matching serpentine trace, due to space constraint, can I do it two times or more under the same trace?

Please have a look at my latest amendment on different pair routing and deskewing.

View attachment Diff_Pair_Deskew.bmp

Any comments on routing issues are most welcomed!

 

[andre_luis]

nelson


I never saw anythink like that serpentine this way.
It could provide a worst effect even than a straigh line.

Anyway, you would to choice some standard specified constraint to sacrifice and I sugest distance ( standards accepts some tolerance )

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[nelsonys]

Andre,

What is your suggestion of amendment for this case? Differential Pair Skew Budget = 0.5mm (I routed using small serpentine) and Group Differential Pair Skew Budget = 5mm (I routed using big serpentine bends).

 

[FvM]

I never saw anythink like that serpentine this way.
It could provide a worst effect even than a straigh line.

I thought exactly the same, before reading your answer. Has the serpentine feature been added by a tool automatically, if so, which one? If you added it manually, what's the underlying calculation? It simply looks wrong, overcompensated by large amount.

 

[nelsonys]

Hi FvM,

Yes I agree with your point. I did not use the tool to generate serpentine trace. The skew budget for each differential pair is 0.5mm, which is quite harsh indeed for LAN setup by our circuit designer in this case. Both sides of the connectors are places asymmetrically which increased the length difference a lot for the differential pair. Regrettably, I was forced to compensate that long in order to meet the 0.5mm requirement.

There's another solution for this problem which I do not know whether it is feasible or not. Instead of using lots of small serpentine according to the design rules, might as well apply a large 'U' on one side of the trace which could make the routing seem nicer. Please advise on this solution.

 

[andre_luis]

nelson,

I supose the measured routed track lengh were performed by the CAD you´re using.
Note that electrical lengh is not necessarily equal to geometric distance.

So, precision obtained with low-angle multi serpentines is less than a unique serpentine.
In other hand, a single seprpentine ("U") will violate differential skew constraint.

My personal opinion is to you adopt a solution between both cases.
Once more, I also sugest sacrifice some lengh specified by standard, according rule tolerance.

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[nelsonys]

Andre,

Could you please explain more on "electrical length is not necessarily equal to geometic distance"?
and also what is the "differential skew constraint" that you are referring to?

In other words, I should apply some tolerance on 0.5mm constraint? Say for 10%, it won't help much in reducing numbers of serpentine I guess.
Primarily, it's the 0.5mm that caused this weird and over-length serpentine to occur.

Thanks.

---------- Post added at 11:35 ---------- Previous post was at 11:25 ----------

Hi Andre,

Do you mean that when the transmission line is electrically short (smaller than 1/4 wavelength), then it is not necessary to match the diff pair so strictly? but this deskewing is definitely for matching timing issues. I think I really have misconception here and consfused a lot.

Please advise.

 

[FvM]

Do you mean that when the transmission line is electrically short (smaller than 1/4 wavelength), then it is not necessary to match the diff pair so strictly?

The objective of intra pair matching isn't primarly to achieve certain transmission line parameters. It's to avoid transformating differential into common mode signals and mainly EMI related. As already mentioned, it seems pretty superfluous for 100 MBit ethernet in my opinion. I wonder, if the 0.5 mm specification is validated by IEEE 802.3 somehow?

I suggest to look at the unsymmetrical (one side meandered) lines in terms of L and C, not just nominal length, which would show the said overcompensation, I assume.

 

[marce]

Hi,
I would try and change the fan out from the BGA to try an equalise the lengths better.
There is a document that covers the above discourse, whether skew or matched lines are most critical, I am still trying to find the releveant paper!
But here is some more nortes that shows the serpentine as not good! Page 5.

Also have a look at this:
**broken link removed**
Right the First Time
Correct me if I'm wrong but 0.5mm equates to about 3.5pS delay!