Amir Yazdanbakhsh
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Hi,
I am trying to synthesize a sequential circuit. Suppose the design has two outputs (out1, out2). I want to define different timing constraints for each of the outputs. By this, I mean for example to put timing constraint 0.5 for all the paths that lead to out1 and timing constraint 0.75 for all the paths that lead to out2. Following you can see my Verilog design:
I am trying to synthesize a sequential circuit. Suppose the design has two outputs (out1, out2). I want to define different timing constraints for each of the outputs. By this, I mean for example to put timing constraint 0.5 for all the paths that lead to out1 and timing constraint 0.75 for all the paths that lead to out2. Following you can see my Verilog design:
Code:
module test(clk, a, b, c, out1, out2);
input clk;
input a, b, c;
output out1, out2;
reg a_reg, b_reg, c_reg;
reg out1_reg, out2_reg;
wire out1_w, out2_w;
assign out1 = out1_reg;
assign out2 = out2_reg;
assign out1_w = ((a_reg & b_reg) | c_reg);
assign out2_w = ((a_reg | b_reg) & c_reg);
always @(posedge clk)
begin
a_reg <= a;
b_reg <= b;
c_reg <= c;
out1_reg <= out1_w;
out2_reg <= out2_w;
end
endmodule