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Hi [USER=688727]@didid[/USER]

First of all, we need more information about your circuit and testbench that you are using:

1. What is the testbench that you are using for your test? Is it an open-loop or closed-loop simulation? (If it is a closed-loop simulation, then your pseudo-resistor might be an issue because it wouldn't give you a correct result in DC)

2. Did you perform any other functional tests for your circuit? What kind of difference do they show, and how significant is the difference?

3. I might be missing something, but I cannot find any traditional current source here... How do you set the bias?

4. Did you pass LVS and ERC checks?

5. It would be useful to see your layout with some comments as well.

Regarding the result, I have a few thoughts:

• Sometimes, during backannotation of the post-extraction results, Virtuoso might show current per multiplier, not for the entire device. This can be checked by measuring power consumption before and after the layout.
• If you are using "R+C" or "C+CC" extraction, it might be useful to re-run your sims with "No RC" - it will give you an idea whether the layout dependent effects are the root cause or the resistance/capacitance of the nets. Please share your "No RC" extraction sims with your layout afterwards.

Hopefully, that helps.