Different results between pre-sim and post-sim

Hi @didid

First of all, we need more information about your circuit and testbench that you are using:
1. What is the testbench that you are using for your test? Is it an open-loop or closed-loop simulation? (If it is a closed-loop simulation, then your pseudo-resistor might be an issue because it wouldn't give you a correct result in DC)
2. Did you perform any other functional tests for your circuit? What kind of difference do they show, and how significant is the difference?
3. I might be missing something, but I cannot find any traditional current source here... How do you set the bias?
4. Did you pass LVS and ERC checks?
5. It would be useful to see your layout with some comments as well.

Regarding the result, I have a few thoughts:

• Sometimes, during backannotation of the post-extraction results, Virtuoso might show current per multiplier, not for the entire device. This can be checked by measuring power consumption before and after the layout.
• If you are using "R+C" or "C+CC" extraction, it might be useful to re-run your sims with "No RC" - it will give you an idea whether the layout dependent effects are the root cause or the resistance/capacitance of the nets. Please share your "No RC" extraction sims with your layout afterwards.

Hopefully, that helps.

Thank you for you kind answer, @sidun.av

First of all, I changed W/L information of some transistors so the simulation results got little different from the first results I applied before.
1. The picture below is my circuit. It is a closed-loop simulation.

It is hard to see but the pin NN and the PP are the inputs for the core amplifier.
In addition, one PMOS transistor is used as pseudo-resistor.

2. I got xf simulation and transient simulation for ac response and the exact value of the voltage from some nodes. The pictures below are the results of the post-layout simulation and pre-layout simluation, respectively.



3. I also developed the bias circuit with current mirroring. You can see the NMOS with the gate name 'VB0'. The voltage about 500mV is applied to the 'VB0' node, so NM2 works like a current source.


4. Yes, of course. I double checked the LVS and ERC errors.


5. The picture below is my layout




I checked the current per multiplier. It was exactly right with what you said. The amount of current flowing showed per multiplier!!
And after I rerun the sims with 'no R/C', the simulation results was same as pre-layout simulation. However, the directions of the current in PM2, NM2, PM9, PM8, NM12, NM11 are opposite as you can see the picture below. Is that okay??

And after I rerun the sims with 'no R/C', the simulation results was same as pre-layout simulation

Click to expand...

It looks like the problem is with RC then...
Could you please share zoomed-in version of your layout? It will be useful if you can do a screenshot of the used layers palette too.

Please, remove the dots while screenshotting - Press "O" and instead of "dots" select "none" in grid control.

I can also recommend checking some internal nodes of your LNA and comparing them with the original schematic behaviour, let's say VON1, VOP1 - I guess they might show you the reduced amplitude as well due to excessive loading (the current in this branch is quite low, but driving gates of CMFB and output stage). If that's true, you can extract all nets, excluding these and repeat the simulation. If the results would be better, that's the root case you are looking for.

I am sorry for the delay in posting the photo.
I changed the schematic of the pseudo-resistor again, so the layout of the pseudo-resistor is a little different.

I don't think your pseudo-resistor is a culprit to be honest...
If you will follow the procedure I mentioned in my previous post, I think it would be more obvious which net is the root cause. When you will start debugging the parasitic capacitance - plate-to-plate is usually dominates down to 65nm, below 65nm it would be mostly fringe capacitance.

Hopefully, that helps.