Different oscillator for FPGA system clock

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shawnmk123

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Hello,

I'm using the 576-4651-ND (Digikey Part Number) for my FPGA system clock.
The part is a differential oscillator. The input voltage is 3.3V. the output voltage swing is .35V.

I don't know what is a differential clock (i've never used it before). Anyways, I'm connecting it to 2 MRCC pins (Positive and Negative) of any Bank in XC7A35T-1FTG256.

What should the VCCO of that Bank be? 3.3V or something else.

Please help.

Thank you,
 

VCCO of the bank should be set to 1.8 for LVDS, or 2.5V for LVDS_25, if you want to use the internal termination resistor (enabled with DIFF_TERM = TRUE, I recommended that you use it for best results).

If you use an external termination resistor you can use a VCCO that is different than the two mentioned but there are various criteria that must be met. Read UG471 - Rules for Combining I/O Standards in the Same Bank, starting at pg 97 if you plan on using a different VCCO voltage.
 

I'm referring to the NetFPGA 1G CML application schematic for building my custom FPGA board.
They are using the kintex 7.
They used a differential 200 MHz oscillator for their FPGA system clock.
(input VCC = 3.3V, output connected to bank with VCCO = 1.5V using a termination resistor).
the IO standard they used was the LVDS.
Did they connect the DIFF OSC (DSC1123AE1-200.0000T-ND) to a Bank with VCCO = 1.5V because the max output offset is 1.4V and pk to pk is 0.350V?

Can I connect the same DIFF OSC to a Bank with VCCO = 3.3V?

Thank you for your help.

- - - Updated - - -


That was helpful to know.
 

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