Different operating conditions in the MV and design libraries

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Hi all!
I want to create Multi-Voltage design in DC. As I understand, I need to use some specific cells for power gates, level-shifters, etc.
The problem is that library for these cells has different operating conditions (names of the op cond in the lib/db file) than library for normal cells, so the question is: how I should use set_operating_conditions command for my design? As I understand, this command does not support multiply op_cond statements, only one op_cond must be defined for the one scenario (correct me if I wrong).

Thank you in advance!
 


Your libraries have to match. If you use libraries that don't match, one of them will be assessed at the wrong corner/opcondition and the results cannot be trusted.
 

Thank you for your answer!
Yes, I understand.
But this is the libraries from one PDK from well-known vendor.
Actually, say, for design library with VDD 1.2V name of the op_cond in the lib file is "op_cond_A". For the MV library with level-shifters from 1.0V to 1.2V there is op-cond name is "op_cond_MV", and the main VDD is 1.0V. How I can use this two libraries together in the same design?
 

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