Different interpretation of SystemVerilog (involves cast, shift, negation)

I have a simulator and a synthesize tool which have conflicting results in the following code / case:

lessthan = ((B << 1) <= B_t'(-N));

lessthan is "logic"
N is "logic [11:0]" and has value 53;
B is "logic signed [18:0]" and has value -26;

B_t is a typedef for "logic signed [18:0]";

The simulated design results in lessthan being 0 / false.
The synthesized design results in lessthan being 1 / true.

Which tool is right? In other words, how should the SystemVerilog be interpreted.
- There is a negation of an unsigned logic value 53, followed by a cast to logic signed, on the right hand side of the equation.
- The left hand side has a shift-left by 1, on an logic signed value -26. I expect this to result in -52.

I think B_t'(-N))) is interpreted differently by the two tools.

What is the correct interpretation? Preferably with reference to the SystemVerilog standard.

Thanks for any insight.

It would help instead of writing

likewise said:

lessthan = ((B << 1) <= B_t'(-N));

lessthan is "logic"
N is "logic [11:0]" and has value 53;
B is "logic signed [18:0]" and has value -26;

B_t is a typedef for "logic signed [18:0]";

Click to expand...

you could write the same in legal SystemVerilog syntax

IEEE 1800-2012 LRM said:

If the expression is assignment compatible with the casting type, then the cast shall return the value that a variable of the casting type would hold after being assigned the expression.

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That means should behave the same as That should result in false.