Different DRAIN CURRENT values in CADENCE.Which one is true?

[andich]

Hello everybody,

Firstly, I use Spectre, mmsim-72, Cadence 5.10.41.

I have an interesting problem. I want to measure the drain current of a nMOSFET; however I get different results based on what I actually look at. Here is what I mean:

1. If I simply click to the drain terminal of the NMOS and plot the transient current, I get one value.

2. If I look at the 'id' variable of"transient operating points" from Analog environment, then I get a different number. It is always smaller, I guess.

My question is where this difference arises from. Is there something not included in "id"of "transient operating points"? Which value should I trust?

I have attached image of my simple circuit. As you may see, in plot it is 11.83p and annotated id is 9.43p.

I would be really happy if one of you guys can help me.

Thanks in Advance.
**broken link removed**

 

[dick_freebird]

Slide on down to the model / macromodel layer, and see
if there are any additional elements that you can't see from
where you're at. For example there may be leakage resistors,
controlled sources, etc. in the macromodel layer.

Cadence' display texts and terminal currents are mapped
to some specific element, but if there's more than one
attached to the terminal than you only see that one piece's
contribution.

I have seen that many times since I do a lot of hokey
macromodels to emulate hokey device behaviors. Like the
FET model doesn't leak enough to match reality, etc.
So I'll add a shunt conductance and maybe a zener for the
(also not modeled) breakdown. But plotting the FET terminal
current only shows the FET itself, not these fellow travelers.

When in doubt, believe the simple element. If I know I
have this sort of issue, I place presistors in legs where I
will be interested in probing current (presistors are LVS-benign,
netlist as shorts there, so I don't have to chase the sense
resistors out of the schematic later).

 

[andich]

Re: Different DRAIN CURRENT values in CADENCE.Which one is t

First of all, thanks a lot dick_freebird. I am stuck in endless documents trying to figure this thing out. Now, you give me some idea.

What I've found is that "id" parameter of operating points (OPPOINT) is called "resistive drain current". I suppose this is related to what you are saying.

I managed to narrow down the problem that it is due to different current flowing from drain to bulk.
Since "id" of OPPOINT is only resistive, I guess when I plot the drain terminal current from simulation results, it includes something else in addition to resistive current.

However, I also found out that "id" parameter includes the breakdown situation which means it includes diode model.

Thus, is it just capacitor model missing in "id"?. I'm still a bit confused.

I am gonna take a look at the macromodel layer first thing in the morning but I didn't quite get how placing a presistor (first time I heard of this) can help me in this situation. Besides, I would appreciate if you commented on what I have described above.

 

[dick_freebird]

Once currents enter a "port", how they may divide and sum
is not "visible" to the graphical design system. Maybe if
you knew all the subcircuit nodes / elements' naming,
you could dig deeper in Spectre. But the intermediate
netlist you see, is not the "real deal" - only the outer skin,
so to speak.

The current that is returned to Spectre, can be mapped
to an element within the FET, you see it as a primitive
but it is not necessarily so - it can be a composite with the
details hidden from view, and not all currents will be reported.

But a simple element (resistor, voltage source, presistor)
has a simple / believable port result, and presistor has the
nice feature that it does not bugger LVS later.

Not really a concern in your present schematic (the voltage
sources serve just as well) but in a more complex circuit
that will proceed to layout, you don't want a bunch of things-
that-will-not-be-present in the schematic to mess up your
netlist match.