Different DC current in Schematic and post-layout simulations

[hosseineslahi7]

Dear experts,
I have designed an LNA in 22nm FDSOI technology with Idc=4mA and Vdd=0.6V. The relevant parameters are in the proposed ranges, however, post-layout shows only 30% DC current (Power reduced from 2.4mW to less than 1mW). Consequently, the gain is too low and NF raised dramatically.

Both DRC and LVS are cleaned but I do not know what is happening in the layout. Has anyone seen the same problem before? Any idea how I can debug it?

Regards
Hossein

 

[jjx]

What kind of extraction have you done for "post-layout"? RC-extraction I assume or do you get the same results for C-extraction only?

If you use RC-extraction, then look for excessive resistances in the netlist. A 100-Ohm resistance would give you a 0.4-V drop, etc.

Play around with thresholds in the extract deck to further debug and find possible culprits for IR drops.

 

[dick_freebird]

To the extent that "IDC" is really time-averaged DC+AC,
your AC gain and low supply current could be all "of a
piece" and due to AC losses along the lineup. An amp
with high PAE means a high part of supply current is
delivered load power, right?

To dig in, and presuming this work is being done in
Cadence, I suggest you make use of the clean
verification and Hierarchy Editor / config view, to
make a lockstep simulation that holds both a
schematic-tree, and an analog_extracted config'd
instance of the LNA, same drives, same loads.
Run it, and probe up / down the hierarchy to
see where things diverge. You can find the net on
the "layout" (extracted) using cross-probe and then
ADE probe.

If it's some other platform, maybe that has similar
resources for defining the netlisting basis, fine grained.