Differences between SiGe process and CMOS

[li-jerry]

Dear all, I was used to be a CMOS designer, but now have to try SiGe process. May I have all the friends' advice about SiGe? For example, the guidelines, the important difference, or somethins about layout, etc. 3X a lot to my dear friends!

 

[hrkhari]

Re: SiGe Process VS CMOS

Hi

SiGe process offers much more higher gain with higher transit frequency, and with less loading parasitics. If you are using the npn transistor the base is doped with Ge which provides higher current gain. The layout requires much more precision in symmetry since there is a current flow at the base, copared to CMOS where there is no current flow at the Gate

Rgds

 

[vfone]

Re: SiGe Process VS CMOS

IBM process comparison:
https://www.research.ibm.com/journal/rd/472/dunn.pdf

 

[lokeyh]

Re: SiGe Process VS CMOS

For CMOS, you can change within and length. But for SiGe, there is less flexibility as there are fixed sizes and the layout of the bipolar is almost standardized.

 

[rfic]

SiGe Process VS CMOS

How can I acquire SiGe's design kit?

 

[selvaraja]

Re: SiGe Process VS CMOS

from layout point of view you must carefull signal path ..avoid making turns for high speed signals ...you less worry about drc rule compare to CMOS ...cause most foundry provide fix layout for SiGe HBT (bipolar).

 

[triquent]

Re: SiGe Process VS CMOS

which technology is the most popular in industry now? And how about their application? ex. CMOS, BiCMOS, Bipolar, or GaAs. Anyone can give an summary?

Hi

SiGe process offers much more higher gain with higher transit frequency, and with less loading parasitics. If you are using the npn transistor the base is doped with Ge which provides higher current gain. The layout requires much more precision in symmetry since there is a current flow at the base, copared to CMOS where there is no current flow at the Gate

Rgds

 

[devrimaksin]

SiGe Process VS CMOS

Of course CMOS is the populat one because it is cheap

 

[devrimaksin]

SiGe Process VS CMOS

BEing able to work with SiGe process is very advantageous, notice 2 thing, first the transconductance
gm=Ic/Vt it changes linearly with the bias current,
and at least 20 times higher than CMOS counterpart for the same bias current.
And small signal gain
gm.ro=Ic/Vt*Vaf/Ic=Vaf/Vt as you can see this value is independent of the biasing condition (as oppose to CMOS), Vaf early voltage in a good process is arround 100 and Vt at room temperature is 26 mV. So the small signal gain that you can get from a BJT is on the order of 4000 (72dB). In practice of course this going to be smaller but it explain the potential of the device. The only bad thing is the low input resistance, but you have
learn proper design structure to circumvent this (so it is doable). Once you fully undestand the capacbility of the device, especially in analog domain, you will start to appreciate it more more
is arround

 

[krashkealoha]

Re: SiGe Process VS CMOS

I had posted this paper, which may be pertinent to this discussion, in another thread.



"CMOS and SiGe Bipolar Circuits for High-Speed Applications"
by Werner Simburger, et. al., GAAS IC Symposium 2003.

Abstract—Recently, CMOS has been demonstrated to be a
viable technology for very-high-bit-rate broadband and wireless
communication systems up to 40Gb/s and 50 GHz. Advances in
device scaling and doping-profile optimization have also resulted
in SiGe bipolar transistors with impressive performance, including
cut-off frequencies of more than 200 GHz. This paper presents
advances in circuit design which fully exploit the high-speed
potential of a 0.13 µm CMOS technology up to 50GHz and of a
high-performance SiGe bipolar technology up to 110GHz operating
frequency. The combination of advanced circuit techniques
and a state-of-the-art fabrication-process technology results in
continuing the upward shift of the frequency limits.

 

[jebi]

Re: SiGe Process VS CMOS

By my personal experience, you'll really appreciate the high gm of
Sige HBT, high current capability so that reduce the parasistic in the
same current requirement. You may often need degenerated resistor
to help the linearity, current mirror matching, lower the noise current.
In LNA design, due to the higher gm, the noise should be smaller inherently.
And, lower LO power requirement for switching function in Mixer. In PA design,
SiGe provide higher power effency due to higher gain.

 

[dini]

Re: SiGe Process VS CMOS

In terms of Ft:

what you achieve with SiGe in a given technology node, you achieve it with 1 to 2 genetation later with RFCMOS.

Remind that RFCMOS is not a pure CMOS technology. It requires several metal layers (6-7) for inductors and special process steps/ and design to reduce noises and increase reliability.

Regarding flexibility on dimensioning and transistor optimization, Sige bipolars can be modelled with "Hicum" physical and scalable model:

have a look on Xmod products: www.xmodtech.com

Regards,