difference of I/O and ESD design between digital and PLL IC

[xihuwang]

PLL's I/o design

Hi:
What is the difference of the I/O and ESD design between digital IC
and PLL IC ?

 

[mikersia]

PLL's I/o design

I/O for PLL (it can be supply IOs, control IOs and analog IOs for external components connections ) should be designed taking into account typical analog considerations such as good noise isolation from digital part of IO ring. So IO for PLL should be done as isolated frame with appropriate glue cells to rest of IO ring. ESD protection could be identical to digital I/O's. Differently from pure digital the I/O for PLL may require direct connection from internal node to bond pad (i.e. analog I/O).