NOR gate transistor level CMOS circuit has PMOS in series from Vdd to output. Mobility of holes is less than mobility of electrons. So, the output load, which is capacitive takes a longer time to charge. If , to compensate for the lower hole mobility, the width of the PMOS devices are increased, then, 1. The gate will consume more area. 2. The bigger PMOS will add more capacitance.