Verilog is most used in the USA and VHDL is used mainly in Europe if I'm not mistaken. I think that Verilog is used by more companies than VHDL.
Verilog is a more user-friendly language, allowing code to be simpler. However, with this simplicity comes a slighlty increased risk of bugs when compared to VHDL.
VHDL is a strongly typed language, meaning that often you have to write a lot of code to do simple things. However, this also means a smaller probability of bugs in your design.
Personally I prefer Verilog because it is easier and the code is more readable. IMO the VHDL strong-typing brings more issues than it solves. Simple tasks like incrementing a variable, perform math operations, etc. often require long data type conversions in VHDL and a lot of code for simple multi-dimension array declaration. In Verilog is simpler, though not perfect. SystemVerilog brings the best of both Verilog, VHDL and C++ but some tools do not support it well.