Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
The target_library specifies the name of the technology library that corresponds to the library whose cells the designers want DC to infer and finally map to. The link_library defines the name of the library that refers to the library of cells used solely for reference,i.e., cells in the link_library are not inferred by DC. For example, you may specify a standard cell technology library as the target_library, while specifying the pad technology library name and all other macros (RAMs,ROMs etc.) in the link_library list. This means that the user would synthesize the design that targets the cells present in the standard cell library, while linking to the pads and macros that are instantiated in the design.
The target library name should also be included in the link_library list. This is important while reading the gate-level netlist in DC. DC will not be able to link to the mapped cells in the netlist, if the target library name is not included in the link library list. For this case, DC generates a warning stating that it was unable to resolve reference for the cells present in the netlist.
The target_library and link_library system variables allow the designer to better control the mapping of cells. These variables also provide a useful means to re-map a gate-level netlist from one technology to the other. In this case, the link_library may contain the old technology library name, while the target_library may contain the new technology library. Re-mapping can be performed by using the translate command in dc_shell.""
link_library is for resolving the references only..so if you are using an instance of a design whose definition is not available in the source path you specify the .db file name and also including the search path in the search_path variable. link is the command used to resolve the functional references in your design
target_library is for mapping your design...your netlist after synthesis can and shall contain only cells from target library
so target is for mapping and link is for resolving functional references..
hello shivram sir,
sir do you mean to say that the target library contains the the transistor technology level information related to the cells in the link library.So when the link library takes a sub-design in a design.the link library would based on the reference and cell names would link to the library cell or design file and send the cell information like pins,delay,ports etc to target library which will be based on technology for which it is written for ,this target library would map the design accordingly.And also later when setting the operating conditions it would tell DC what is to be done for the operating condition.
Sir please tell me if my understanding is correct,actually i am getting confused with these libraries.
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.
