Difference between Single ended clock and Differential clock

[karthik gunda]

Hi,

I am new to FPGA. Anyone please explain me the difference between single ended clock and Differential clock.


Thanks,
Karthik

 

[mrflibble]

This should get you started: https://bit.ly/1fBmJX8

 

[shahulakthar]

Differential clock consist of SYSCLK_P and SYSCLK_N are connected to a differential clock oscillator.

Differential Signaling is not sensitive to SSO noise.
A differential receiver is tolerant of its ground moving around.
If each “wire” of pair is on close proximity of one and other. electromagnetic interference imposes the same voltage on both signals. The difference cancels out the effect.


Single ended clock only contain SYSCLK_P pin connected to a clock oscillator.

Single ended signal subject several means of distortions and noise.