cyboman
Member level 4
i'm slowly learning digital design and verification. i'm currently reading a book on OVM (very difficult read) and it states that there might be differences when simulation is used vs emulation. at this points i don't care what is the difference in results. but i care about what is the difference? to me simulation and emulation meant exactly the same thing. and it seems to me that i misunderstood it. i would really appreciate an explanation of what is the difference between simulating the design and emulation the design.
any help is appreciated
any help is appreciated