difference between post synthsis, post translate post map and post par simulation

Hi every one
I want to know difference between behavioral, post synth, post translate post map and post par simulations
I have already gone through earlier discussion on this forum.
So I got to know that behavioral simulation doesn't consider any delay, post map contains propagation delay and post par contains both propagation and routing delay. am I right.?
Now I am not clear with post synth and post translate simulation.
when I have done post synth and post translate simulations with dut_synthesis.v and dut_translate.v i got same result with small delay in output. As till translate we are not having sdf file we can not use .sdf for post translate simulation (as one discussion suggest to use sdf for post translate simulation) .
Now can anyone explain which are those delays in result?
and why post synth and post translate results are same?


thanks

seeker_123 said:

So I got to know that behavioral simulation doesn't consider any delay, post map contains propagation delay and post par contains both propagation and routing delay. am I right.?

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That pretty much sums it up.

seeker said:

Now I am not clear with post synth and post translate simulation.

Click to expand...

Synthesis would be checking the logic that was generated by the synthesis tool, so loops are unraveled, logic is examined and logic optimizations occur and a optimized netlist is produced.
Translation then maps the netlist into corresponding library components, but from what I've seen this really only happens if you feed it a edif netlist, which doesn't have the library components in the netlist. In the case of XST & translate, the translate step is more of a linker step linking multiple ngd/ngc file together into a single library netlist.

seeker said:

when I have done post synth and post translate simulations with dut_synthesis.v and dut_translate.v i got same result with small delay in output.

Click to expand...

In the case of Xilinx (probably Altera and others) the library components in the simulation library have #delays all over the place. (Don't get me started on the issues I have with the way Xilinx codes their unisim libraries, let's just say I've had mismatches between simulations and actual hardware on DDR output registers in the past).

What is your purpose for doing post synth and post par simulations? These should only be needed if you have a problem that doesnt turn up in behavioural simulation. If you have a fully synchronous design, then most post synth or post -par simulations are not required (in 10 years in industry, I have never run a post synth or post PAR simulation on code destined for FPGAs). Usually you need good front end design, a good test bench and good timing specs.

The only time I can really see the need for the extra sims is when you have async logic (usually a bad idea) or some complicated and timing critical interface (that you should have good timing specs for anyway).