Difference between NMOS/PMOS with and without Deep Nwell

[hafis.m]

I there any difference between NMOS/PMOS inside DNW and outside DNW in terms of IV characteristic like IdVg, IdVd, gm?
Can I use a normal NMOS to run ADE simulationto get IdVg of an NMOS inside DNW or vice versa?

 

[deep_sea]

I would assume they would behave almost the same. If you have a device inside DNW, this means you have the option to connect its bulk terminal to a different voltage and not necessarly to the most (positive or negative) terminals.
Why cannot you use NMOS in DNW directly in simulation?

 

[dick_freebird]

If deep nwell is -only- deep and does not abut the
surface, then it can isolate a P pocket for NMOS which
is no different than the plain epi / bulk. There would be
a regular NWell for PMOS which is different. PMOS in
deep Nwell without regular NWell would probably be a
depletion-mode PMOS.