Difference between core power pad and IO pad

[RuihW]

Hello everyone,

I'm designing the IO ring with TSMC 0.18um PDK. In my design, the majority of the FETs are 1.8V. But there are some 3V FETs that need 3V for gate (they still use 1.8V for Vds). The 0.18um PDK has two pads: PVDD3A and PVDD3AC. Which one should I use for VDD? My understanding is that since the core is based on 1.8V, I should use 3AC. Am I correct?

 

[rafauy]

What does the documentation say about the A and AC variants? Whats the difference between them?

 

[RuihW]

What does the documentation say about the A and AC variants? Whats the difference between them?

The "C" stands for core. According to the databook, the A variant is for IO voltage (3.3V) and AC is for core voltage (1.8V). After reading the documents, I think I'll use the AC variant for VDD/VSS, and place power-cut cells to isolate the 3V pins.

 

[EV-ffyy]

Hello,

For your design, if the majority of the FETs are 1.8V and you have some 3V FETs that require 3V for the gate while using 1.8V for Vds, you should consider the specific requirements of your design and the characteristics of the pads.

Given that your core voltage is based on 1.8V, using PVDD3AC would be appropriate. The PVDD3AC pad is typically used when you need to interface with core voltages of 1.8V while still providing 3V for specific IO requirements.

 

[dick_freebird]

Sometimes (and especially for analog) you might want to
use 3V FETs and situate them in the core area. The PVDD3AC
might be meant for "Analog" (quiet) core power and PVDD3A
for I/O-ring-located analog pads, where the PVDD3 or PVDD3D
I/O rail must be suspected of being trashy?

Of course I don't know if all N alphasoup permutations are
in the TSMC kit, just speculating - and as designer the choice
is largely yours, although built in inherited connections may
deliver a starting opinion from the logic cell libraries that will
bother you in verification if you pick wrong, to start.

 

[RuihW]

Hello,

For your design, if the majority of the FETs are 1.8V and you have some 3V FETs that require 3V for the gate while using 1.8V for Vds, you should consider the specific requirements of your design and the characteristics of the pads.

Given that your core voltage is based on 1.8V, using PVDD3AC would be appropriate. The PVDD3AC pad is typically used when you need to interface with core voltages of 1.8V while still providing 3V for specific IO requirements.

Thank you. My confusion between the 3AC and 3A is the voltage rating. I assume that I can supply 1.8V to a 3A cell but cannot supply 3V to a 3AC cell, or the 3AC cell's diodes may be damaged. Is this correct?

 

[dick_freebird]

I think you need to go to the PDK docs for that.

A simple guess would be that "3AC" is "3V, analog
domain, core" but who's to say besides the foundry
or someone who's gone down this road far enough?

"Diodes" aside from the inherent S, D to B in each
FET, are not "core" features unless an antenna diode
is placed. At 3V or 1.8V you will not break down any
diode but could see forward conduction if anode is
3V and cathode, 1.8V. Supply transitions sequencing
are also a question. Step back and make yourself a
cheat sheet table of this stuff, to get your mind right.