difference between clock buffer and ordinary buffer

[sreenu236]

what is the difference between clock buffer and ordinary buffer.

 

[srkumar81]

clock buffers are designed in such a way that the slew and load will be better than ordinary buffers.

 

[sameer_dlh25]

clock buffer have balance rise/fall for output and balance transition.

 

[Fawad Elahi]

buffers are usually used for storing data(information). now the main difference between a clock buffer and ordinary buffer is its synchronization between the input and output.

 

[shiv_emf]

clock buffers r used in CTS
ordinary buffers can be used anywhr ..for restoring purpose or to add delay
Shiv

 

[xinsu]

normally,clock buf have more power cost than ordinary one.

 

[rakesh1234]

Clock buffers have rise delay and fall delay nearly equal in order to reduce clock edge skew.
While ordindary buffers do not have this facility.

 

[lever]

clock buffer is optimized for some requirements of clock especially. (skew, power and so on)
The clock buffer is symmetrical cell. It means the rise delay equal fall delay nearly.

what is the difference between clock buffer and ordinary buffer.

 

[lohi21]

Hi All,

Suppose if we use normal Buffers/Inverters in place of Clkbuff/clkinverters, What would be the outcome?

One thing is because of the difference of synchronization in fall/rise time, setup/hold time violations can happen. But then again this can be correct by various text book methods right.

Please let me know.

Regards
Lohi

 

[artmalik]

I know this is an older thread but it is something which I want to put forward my thoughts for a person who might read this thread in future.

Clock buffers are balanced in rise/fall time.
Reason : If you dont have equal rise and fall time then you will have a duty cycle distortion in the clock. If you provide 50% duty cycle clock the output should also have 50% duty cycle.

clock buffers tend to have a different P/N ratio( in lower technologies ) they are coming to same as a normal gate PN ratio. This is done because the gates are designed for equal rise_delay and fall_delay while clock buffers are designed for equal_rise_transition and equal_fall_transition.

clock buffers have more activity during their life cycle so the ouput pin is made thicker ( for signal EM) and many times a strap of M2 is added on top of the output pin to reduce the current density.

Normal buffers are for delay generation ( mainly for hold fixing) . Many times they are two stacked nmos/pmos to make a weak inverter. The main goal is get as much delay as possible for hold fixing.

there are many other small small details ....but over all this covers the main aspects of the difference between clock buffer and normal buffer.