Difference between blocking and nonblocking in Verilog

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ruwan2

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Hi,

I am new to Verilog. Although there are already posts talking about blocking and nonblocking on line, it is still not sure to me on a specific example. I see one hand-out as:


It has "y=", but it shows non-blocking in the legend below. "y=" is a typo?

Then, I simulate this simple module in Modelsim. I do not see any difference with both "y=" and "y<=". Is this true (no difference here) for both simulation and synthesis?

The above example is from the link:
**broken link removed**

on slide 7 of page 2.


Thanks,
 
Last edited:

In the case you show there will be no difference between using blocking and non-blocking, but it's inadvisable to use a non-blocking assignment in a combinational always block.

Unfortunately I don't have the link to a very good paper that showed the differences between using blocking/non-blocking in combinational/sequential always blocks and what the result of synthesis/simulation would give. The end result was there are gotchas that can occur if using blocking assignments in sequential always blocks and using non-blocking assignments in combinational always blocks.

So for best practices:

combination always blocks, use blocking assignments, infers combinational logic:
Code: 
always @ * begin
  y = (a | b) ^ c;
  z = y & D;   // equivalent to having written: z = ((a | b) ^ c) & D;
end

sequential always blocks, use non-blocking assignments, infers registered logic (flip-flops)
Code: 
always @ (posedge clk) begin
  y <= (a | b) ^ c;
  z <= y & D;  // equivalent to having: z = ((a(-1) | b(-1)) ^ c(-1)) & D(0); (-1) old value of a, b, and c that make up current value of y(0) and the current value of D.
end

Try these examples with different combinations of blocking/non-blocking and you will see differences in behavior.


Regards
 
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    ruwan2

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Nope, that's not the one. The page I ran across had some very nice diagrams and quadrant based tables of the various combinations nb-comb, nb-seq, b-comb, b-seq. with nice big red slashed circle (\) over the combinations that shouldn't be used. With examples of why they shouldn't be used.

I think it may have been a Verilog coding guideline handout done by a university professor, but it's been a while since I ran across it so I might not be remembering correctly.
 

hi
plesae correct me if i am wrong
try this code
Code:
Code: 
always@ (a || b) begin
 
  e = b+a;
  d = e*b;
  $monitor("d==%b",d);
end

give b=1,a=0,c=0;
if u give blocking statement then only it will work otherwise it give x value
 

Why do I need to try it? I already know it's combinational logic and requires blocking assignments.
 

ads-ee said:
Why do I need to try it? I already know it's combinational logic and requires blocking assignments.
Click to expand...

its not the replay to u adds-ee .its to ruwan.
really sorry for posting like that.i should have use quotes. actually iam new in this forum..
 

dipin said:
Code: 
always@ (a || b) begin
Click to expand...

This isn't correct, || is a logical OR operation. Sensitivity lists in Verilog are separated by either or or , not ||, regardless you should use * for combinational always block.
 
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    dipin

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ads-ee said:
This isn't correct, || is a logical OR operation. Sensitivity lists in Verilog are separated by either or or , not ||, regardless you should use * for combinational always block.
Click to expand...

thanks for the correction
 

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