vlsi_006
Newbie level 4
synthesize translation mapping
Hi,
What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the implementation phase, in xilinx ise. Please explain the difference between synthesis and implementation in xilinx ISE
Hi,
What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the implementation phase, in xilinx ise. Please explain the difference between synthesis and implementation in xilinx ISE