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diff b/w synthesis and implementation in xilinx ISE

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vlsi_006

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synthesize translation mapping

Hi,
What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the implementation phase, in xilinx ise. Please explain the difference between synthesis and implementation in xilinx ISE
 
what does synthesis process do in xilinx ise

synthesis does not include translation and mapping. Implementation includes translation, mapping and Place &Route.

check xilinx documentation to learn more about the differences.
 
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    ivlsi

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