diff b/w synthesis and implementation in xilinx ISE

[vlsi_006]

synthesize translation mapping

Hi,
What is synthesis process actually doing in Xilinx ISE?I am using xilinx ISE and as per my understanding, synthesis is a process where we do translation, mapping and optimization to get a netlist. But why r we doing again translation and mapping in the implementation phase, in xilinx ise. Please explain the difference between synthesis and implementation in xilinx ISE

 

[tariq786]

what does synthesis process do in xilinx ise

synthesis does not include translation and mapping. Implementation includes translation, mapping and Place &Route.

check xilinx documentation to learn more about the differences.