Die Size and IC Package

[FreshmanNewbie]

I would like to gain a better understanding of IC package lead inductance and on-die capacitance.

For a physically larger IC chip, would the on-die capacitance generally be higher due to the reduced distance between the pad on the die and the corresponding pad on the IC pin lead? Additionally, would the package lead inductance be lower because of the shorter connection length between the same pad on the die and the IC pin lead?

Conversely, for a physically smaller IC chip, would the on-die capacitance be lower, while the package lead inductance is higher?

Could you confirm if this understanding is correct? Any visual representations or diagrams would also be helpful for clarification.

 

[dick_freebird]

Your transistor -on-die to pin-on-board path has several. constituents. Different materials but that affects R more than L.

Core to furthest pin distance follows pkg outline, so does inductance (zigs and zags aside). Modern pin array and flip chip packages are a major departure from this paradigm though.

Use 1nH/mm and decide whether you care in your application context.