DFT

[CVAGHASIYA]

Why we get scan chain blockage even we have fixed pre DFT DRC in Scan?

 

[dick_freebird]

DRC is layout design rule check, in my world. Has
nothing to say about whether the electrical design
functions as you'd like, only that you have not
broken physical "don't do that!" rules. You can still
find plenty of ways to fail without putting polygons
too close to each other.

Seems to me you'd follow the chain trying to find
where there's a break, or a logical meddling with
scan data or scan clock. Like the wrong sense on
a scan FF's mux, clock gating applied to SCLK or
like that.

 

[oratie]

It is DFT DRC, not layout DRC.