[DFT] Should the Spare Gates be included in the Scan Chains?

[ivlsi]

Hello All,

Should the Spare Gates be included in the Scan Chains?

After Scan Insertion and running ATPG as well as functional vectors, how can I summarize the faults coverage?

Thank you!

 

[hariharan.gb]

Even i thougt of asking this question, thanks for posting.

Before that what is this spare combo cells pack, what are all its composites, and where it will placed in a chip? How its composition looks like? will they fuse it when needed as in FPGA? or a combinational back present is reused? if so what are all the minimal and maximal logic i can have there? will i have a FLOP there? if so how i will apply clock for it?

A real picutre of what it is will be great answer? friends help replying?

Hariharan GB

 

[ivlsi]

So, should the spare FFs be included in the scan chains? Thank you!

 

[iwpia50s]

Spare flops are usually not included in scan chains, the D pin is usually tied low. You may want to have the clock pin connected to a clock but in some cases you want the clock pin tied off as well. You should have some spare flops in each clock domain so the flop load is already accounted for in CTS.

Remember, spare flops are in the design for ECOs, if you have to use a spare flop you are changing functionality because it is wrong somewhere. This means the scan results will now be different, so you add the "used" spare flop in the scan chain and regenerate the vectors.

 

[hariharan.gb]

Yes i agree, that the spare cells would be some where present in a CHIP, which doesn't initially put up in a scan chain.
Once an ECO is needed and by that time, we use this spare cells, flops, and put into the scan chain as well, and regenerate vectors for ATPG.

with this i have new doubt born,
whether we have some geometry pre fixed by a Top level designer to place these spare cells or flops in our CHIP, because we dont see a spare in pre_layout Netlist. Am i right?

So, we do have a extra area (small/large - depending on the spare cells) to be present in a CHIP. My pre layout AREA Report will not cover this spare cells intially, but after Layout has inserted, it accounts for area? Will this doesnot disturb my chip size, in terms of area? (later we can discuss abt power). Can any one help on this plz?

Hariharan GB

 

[ivlsi]

You may want to have the clock pin connected to a clock but in some cases you want the clock pin tied off as well

When is better the CLK pin of the Spare FFs tied off?

---------- Post added at 14:43 ---------- Previous post was at 14:00 ----------

Again regarding the Spare FFs...
Should they be already scannable? Should their SI & Q pins be connected to the scan chains and just D-pin tied to a constant value?
Thank you!

 

[hariharan.gb]

To best of my knowledge i am sure, that we don't put a Spare FF/gates in a scan chain, until it is a spare flop/cell.
Once when it decided that we want to use this spare flops, we make ECO for both functional replace and scan replace and then finally a new ATPG vector pattern would be generated...

Please anyonc correct me if i am wrong ?

Hariharan Gb