DFT scan insertion querry

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abc_81

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Hi ,
I am working on scan insertion. I have some querries on the same.
My understanding is lockup latch is not needed when we have negedge flop followed by pos edge flop. But when we have pos edge flop followed by neg edge flop, can I use lockup latch between pos edge -> lockup latch -> neg edge ? Will this work ?
or lockup latches are used only between cross clock paths ? Please clarify
 

to be specific, I wanted to know if we can use lockup latch between pos edge flop and neg edge flop in a single scan chain or lockup latch should be used only between different clock domain ?
 


Hey,

Lockup latch are used as a synchroniser between two flop from different clock domains (asynchronous clocks) along the scan chain and add in the SI path.

There is a switch in RTL complier to mix compatible clocks in a scan chain for posedge negedge launch capture and if they are of synchronous clock same frequency or frequency as a multiple of the same number, you can apply a multicycle path exception while timing them.
 

i think the query here is not on mixing clock domains but for same clock domain if there are pos and neg edges if a LuL will be added in a single chain.
This is what i understood and yes this is possible as well.

Although in such a case it is good to have all neg flops together and all osedge flops together and then have them in a single scan chain with this we can have the a control on the LuL that will be added
 

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