DFT scan clock

[doia]

Hi, I am learing DFT. I have a question about dft scan clock.

Dft clock is defined as follow.

create test clock -period 100 -waveform {45 55} clk

sef_dft_signal -type ScanClock -port clk -timing [list 44 55]


I wonder why clock waveform is set as 45 55 instead 0 50.
Is there anyone who can help me understand about scan clock? No matter how much I search, I don't know why.
Thanks.

 

[rxp]

this command is used for explicitly defining test clock in the design.
here you are defining ScanClock Timing as {45 55}.This waveform definition consists of two values: first rising-edge arrival time and then falling-edge arrival time. this is for multiplexed flip-flop style.
here you have 100ns clock period (which is by default), for your return-to-zero clock during that your positive edge of the clock will arrive at 45ns and your negative edge of the clock will arrive at 55ns.
scan clock is always slower than the functional clock, for more understanding please refer fundamentals of clock period, clock duty cycle and clock frequency and you will understand.
if you don't want to define explicitly then use -infer_clock with -create_test_protocol and tool will take default timing for whichever flop style you are using.

 

[ThisIsNotSam]

These numbers are a property of the design, there is no other reason I can think of why 45-55 was chosen. In theory, 0-50 works.

 

[rxp]

These numbers are a property of the design, there is no other reason I can think of why 45-55 was chosen. In theory, 0-50 works.

Yes definitely in the theory it could work, and the numbers are given for the design, so it differs for each design. you can take {55 65} or {55 75} also.
but think about is it really necessary as you are designing a chip that is designed to work at low power?
minimum clock on period required for scan clock is given as default value, but if you put on clock signal for 50ns , then even in testing mode your system will consume much more power than required. So unless power consumption is not one of your primary concerns, then go for it!
correct me if i am wrong somewhere , much appreciated.

 

[ThisIsNotSam]

power consumption is proportional to the number of clock toggles, not when they happen within the period. so 55 65 and 55 75 are virtually the same if the period is 100.

 

[rxp]

power consumption is proportional to the number of clock toggles, not when they happen within the period. so 55 65 and 55 75 are virtually the same if the period is 100.

this is called dynamic power consumption which depends upon activity factor and clock frequency but i am talking about static power consumption of system

 

[ThisIsNotSam]

this is called dynamic power consumption which depends upon activity factor and clock frequency but i am talking about static power consumption of system

you never mentioned static power, but whatever. please tell me why would test-related static power matter at all?

 

[rxp]

you never mentioned static power, but whatever. please tell me why would test-related static power matter at all?

i am definitely newbie in this field so i need to look into that furthermore