[DFT] Scan chain stitching by DC-Synopsys

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ivlsi

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Hi all,

How the scan chain stitching might be done by DC-Synopsys? How does the tool knows the order of connection the flops into a chain without knowing the physical location of these flops? Will it connect them in A-B-C order according to their instance names?

Is there a sense to stitch the flops during Logic Synthesis or it ALWAYS should be done by BackEnd tools?

Thank you!
 

Depending on the logic cone it decides the order.
Logical synthesis does have DFT compilers which does scan stiching.
 

Depending on the logic cone it decides the order
Click to expand...
Could you please give more details? What exactly rules does the tool use in order to decide on the stitching order?

Is it practical to do stitching by Logic Synthesis tools or it should be always left for the BackEnd tools?

What BackEnd tools can do scan stitching?

Thank you!
 

Back end tool does reoredering and restitching in timing closure stage.
 
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    ivlsi

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Hm... Is timing closure done by FrontEnd or BackEnd tools? What BackEnd tools are used to check/fix the timing?

If BackEnd tools do reoredering and restitching then why to do stitching during Logic Synthesis?
 

Dft timing is done normallly only in backend. Backend tool reorders and restiches flops in the same chain, not cross chains. So it requires front end to give stiched scan chain and scandef file.
 
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    ivlsi

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Thank you RCircuit for your comment! But I still don't it catch for 100%...

FrontEnd tools are usually involved for the Logic Synthesis (let's say RTL-to-Gates + Gates Manipulation (meeting timing/area/power)).

As for the Scan Insertion, neither RTL-to-Gates nor Gates Manipulation involved (besides regular flops to scanable ones replacement)... So, why not to leave the whole DFT insertion phase for the BackEnd tools?

Does DFT Compiler insert some additional logic in the Netlist (support to SI, SO ports, Test Modes, etc)?

As for the LockUp Latches, should they be inserted manually in the RTL code or the tool (which one?) insert them?

Thank you!
 

I usually do Scan Insertion in DC Compiler because there is easy way how to fix all violations, do changes in vhdl files and so on. Do this in Encounter would be a pain.
 

Rules used by DC to do scan stitching is Dictionary Based.
 

Rules used by DC to do scan stitching is Dictionary Based
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Could you explain please? What does it mean "Dictionary Based"?
 

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