[DFT] Scan Chain Diagnosis for simulation mismatch.

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maulin sheth

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Hello All,

I am facing one problem in scan chain diagnosis.
I got only 1 mismatch during with timing gate level simulation.
For that mismatch I know only these things :
Failing time : 7769000ps,
pattern no ,scan in and scan out port.
My scan chain contain the 4000ffs so how can I know that for which ff, the simulation is failing?

Is there any way for debugging in such a way that we can know the scan cell number with the help of timing of mismatch?

Thanks & Regards,
Maulin Sheth
 

In gate level simulation with timing you can look into the log where timing violation has happened.
Which tool you are using to simulate ?
 

I am using Synopsys VCS for simulation.
Actually there are so many timing violations,but all violations are also in other patterns and those are passing...actually I want to know that, If i know the timing, thn how can i know that for which scan cell it is failing ?
What I am thinking is that, the pattern`s failing for capturing, so how can I know the Scan Cell location as DFT is mostly used for the this purpose only?
 

dump the waveforms of scan out and scan enable pins. Point the cursor at the time at which you have the mismatch. Use another cursor to point on the previous rise in scan enable(beginning of the scan unload). Calculate the time difference between the two time stamps. Now divide the time difference by the time period of scan shift frequency. If you can analyze what I just explained, you will have the scan flop number(counted from scan out port) at which you are finding the mismatch. Now the job is check the value of this flop in the capture phase. And analyze the Fan-in cone for the cause of the mismatch.
 
Well, when I faced to a scan simulation issue:
1- I run the simulation without timing annotation, which confirm that the patterns is "functional" versus the netlist, and will confirm that the model used to generate the patterns is the same as used for the simulation. In our design, I have a analog component, and normaly all outputs of this module need to be defined as unknow to avoid and mistmatch.
2- I run STA in scan mode only, I mean, during the STA session, I only defined the scan clock and I used the set_case_analysis to forced the chip in scan mode, and I check there is no violation.
3- When you generate the verilog test-bench to simulate the patterns, check you can not add some features to output more details during the simulation... Usually you should be able to simulate only from pattern x to y, and you do not need to restart from 0.
 

Which tool you are using for pattern generation?
TetraMAX usually writes to console somethig like this:
" %0d %0s %0d (exp=%b, got=%b) // pin %0s, scan cell %0d, T=%t"
where 'scan cell %0d' shows you which cell in your chain is failed.
Not sure about Encounter Test or FastScan console diagnostics.

Also if you have a lot of timing violations it could result to a test failure on ATE. Most of the violations can be masked for current pattern and therefore will not detected (unless you are using cell-aware ATPG). Ideally, you should avoid any of the timing violations during scan test.
 

Hello kornukhin,
I am using the TMAX, but done simulation through VCS.
So in vcs log, it is not indicating the scan cell number.
Is there any switch/option in vcs, so I can know the scan cell number?

- - - Updated - - -

And anyone know how the parallel patterns are worked during simulation?
What are differences between parallel and Serial STIL patterns?
From STIL patterns, how can we know that, this is serial pattern or parallel pattern?
 

Is there any switch/option in vcs, so I can know the scan cell number?
Click to expand...
I have used following commands to generate testbench file:
Code: 
write patterns ./net/tb_dft_p.v -format verilog_single_file -replace -parallel
write patterns ./net/tb_dft_s.v -format verilog_single_file -replace -serial

And anyone know how the parallel patterns are worked during simulation?
Click to expand...
Parallel simulation allows you to avoid long load-unload procedure during scan test. Simulation time is shorter.

Basic example:
Assume you have 1 chain with 100 DFFs.
Serial simulation:
You need 100 cycles to load scan data and 1 cycle to capture result.
Then 100 cycles to load new data (and get calculated) and 1 cycle to capture result.
and so on.
Parallel simulation:
Instead of 100 cycle load, there is 'force' which load desired values to DFFs. 1 cycle for calculation.
Read result, 'force' new data, 1 cycle capture.
and so on.
For 300 patterns you will need 300*100+300*1=30300 clock cycles for serial and 1*100+1*100=200 clock cycles for parallel simulation.
Hope it helps.
 

Hello Kornukhin,
I have a doubt in Parallel i.e. how unload procedure is done in parallel patterns...because we have only one observe pin..so if we want to see it in waveform thn how can we see?
and same thing for loading also..if I want to see simulation waveform, than how can I see this as we have only single pin at top level.
 

Parallel patterns is for simulation purposes only. You can't use this test on ATE.
For simulation you will not see input/ouput waveform on test pin. TMAX testbench forces all scan-DFFs to states equal to loaded pattern and then (after capture) compares scan-DFFs outputs with unloaded pattern.
If you want to see waveform use serial patterns. Alternatively, you can send to waveform scan DFFs and check their values at waveform.
 

So we can not see the waveforms of parallel patterns at the top level pin?
Click to expand...
Yes.

Means I have to seen this at each and every flop?
Click to expand...
Also yes.

Basically, parallel is for 1-st check that patterns functionally correct and debug (violations in scan chain shift register will not be detected). Serial for sign-off.
 

Thank you very much....
Because my patterns are parallel ...so How I can know the scan cell for particular time for simulation mismatch? as described in the first thread i.e. question of this thread.
 

I introduced some error into my netlist: iinversion added for input IN2 instance U424.
Run simulation.
Error found. Scan cell reported.
Then I opened parallel verilog testbench. Searched [20], and find scan cell information " force dut.control_observe_register_836_TDGO_reg.SI = LOADSH0[20];".
So cell 'control_observe_register_836_TDGO_reg' is what you need.

 

Hi,

Isn't it 300*1+300*1 for parallel simulation?

As there are 300 patterns and you one cycle to load and one cycle to capture.

And one more question. How does the unload happens? does the simulation tool reads directly from the o/p of scan flops?
 
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