DFT question and answers

1. Why we do simulation, even though we generate the patterns on the same scan stiched netlist. What are we expecting from simulation, as it is not the actual hardware we are testing?

2. Why people prefer doing serial simulation though it takes very long time compared to parallel simulation. Tester doesn't support parallel simulation. Still we don't prefer parallel simulation on the netlist, why?

3. what are the disadvantages of the MBIST on the chip other than the extra logic overheard?

4. Why the coverage for the transition faults is always less than Stuck-at faults?

5. Will MBIST be part of Scan logic?

6. How do we deduct to a particular net or node from a mismatch on the tester?

7. What are the main things to look for to improve the coverage?

8. why latches are made transparent during scan?

9. what is the % overhead of the MBIST logic?

10. what is the typical vector count which gives the maximum coverage?



Can anyone post few more DFT questions typically asked in the interviews with answers if possible.

Thanks
Srikanth

1- well during ATPG we use some models, and during simulation other one, the ATPG could generate wrong patterns due to inconsistency in the model.
2- with serial simulation, you check also the worst hold time constraints.
3- hardcoded Bist is limited to a type of checks, if you need to extend or reduce it, you could not.
4- well you do not check the same stuff, no?
5-no
6-the ATPG tool has normally a diagnose mode, you provide which patterns was different and the ATPG will indicate which or what could be the source of the problem.
7-to improve the coverage, you could report the uncovered faults, and after you need to analysis this list.
8-which latch?, for the latch used for clock gating, need only to be transparent during the shift phase, during the capture, this one could used the functional mode, to improve the coverage.
9-that depend of the MBIST strategy, I means, did you want to have a BIST engine for each memory, or for a group....
10- too large question, that depend of your design, I means ratio combinational versus flop, and which coverage you want to reach?

Hi RC,
I dint understood your reply to the question 4. Why at-speed faults coverage is less than stuck-at faults coverage?
Other than the set/reset logic which is not tested in transition faults, any thing else which are not covered during transition tests?

rca want to say that..when you use different fault model, you target the different different fault....means you are checking different faults by Transition and Stuck At....so how the fault coverage should be same?
The faults in false path also not covered by transition test...
I think you now clear it..

Thanks Maulin and rca.
I thinks multicycle paths also not covered in transitions faults. Is that right?

This all things are totally depends on design....

Just a comment on the rca's answer:
3. Some EDA vendors do provide the flexible Soft programmable BIST controllers. You can program the Algorithm of your choice on the silicon. Again it comes with a considerable area overhead. But other than BIST do we have any other way to test the memory? (not the functionality, but the wide range of memory faults)