DFT logic auto insertion

[fragnen]

In a design we put logic for DFT and we call it design for test. For example we place AND gates in design to detect stuck at 1 fault.

What are the tools which can auto insert this kind of DFT logic in rtls or in netlist and in which phase of a design flow these kind of DFT logic can be auto inserted using such tools?

 

[aliarifat794]

You can try Synopsys DFTMAX ultra.

 

[D.A.(Tony)Stewart]

Back in the early 80's we had one product which was a quad dual-ported SCSI HDD controller with quad I/O host ports. It used 4 bit-slice CPUs for operation and an 8 bit uC with full port readback for DFT. The code was about 3 cm thick of fanfold paper. This display code included both fault detection and fault isolation. This was long before embedded logic DFT communication.

Another example I have used is a motherboard for Telephony , Modems, Video in an ISDN WAN which performed loopback on every port during power-up for DFT with fault detection and isolation > 98%.

So in your design spec you must be aware of every possible fault for detection and isolation with correction possible with redundancy and decide what % of all possible faults you wish to detect based on the consequences and cost of repair/replacement.

Now these days DFT with higher complexity logic has taken on a new meaning with many rules on timing, metastables but also must factor tolerances to threshold from datasheet variances, supply voltage and junction temperature gradients with ambient.

Many of these functions are built into expensive software families.

I have not evaluated these but found a list in 10 seconds on the web. (warning, there may be bias from the source but is defined by the tracxn score algorithm)

DFT Microsystems - 229 Competitors and alternatives in Apr 2024 - Tracxn

DFT Microsystems has 229 active competitors. Competitors include Synopsys, Cadence.

tracxn.com

 

[fragnen]

Back in the early 80's we had one product which was a quad dual-ported SCSI HDD controller with quad I/O host ports. It used 4 bit-slice CPUs for operation and an 8 bit uC with full port readback for DFT. The code was about 3 cm thick of fanfold paper. This display code included both fault detection and fault isolation. This was long before embedded logic DFT communication.

Another example I have used is a motherboard for Telephony , Modems, Video in an ISDN WAN which performed loopback on every port during power-up for DFT with fault detection and isolation > 98%.

So in your design spec you must be aware of every possible fault for detection and isolation with correction possible with redundancy and decide what % of all possible faults you wish to detect based on the consequences and cost of repair/replacement.

Now these days DFT with higher complexity logic has taken on a new meaning with many rules on timing, metastables but also must factor tolerances to threshold from datasheet variances, supply voltage and junction temperature gradients with ambient.

Many of these functions are built into expensive software families.

I have not evaluated these but found a list in 10 seconds on the web. (warning, there may be bias from the source but is defined by the tracxn score algorithm)

DFT Microsystems - 229 Competitors and alternatives in Apr 2024 - Tracxn

DFT Microsystems has 229 active competitors. Competitors include Synopsys, Cadence.

tracxn.com

The link provided the name of the company and not the name or the tools? Can you please provide the name of the tools?

--- Updated May 9, 2024 ---

You can try Synopsys DFTMAX ultra.

Does it mean DFTMAX ultra will automatically insert DFT logic for various fault models?
Will this tool capable to insert DFT logic automatically to make fault coverage and test coverage more than 99% ?

 

[D.A.(Tony)Stewart]

The link provided the name of the company and not the name or the tools? Can you please provide the name of the tools?

--- Updated May 9, 2024 ---

Does it mean DFTMAX ultra will automatically insert DFT logic for various fault models?
Will this tool capable to insert DFT logic automatically to make fault coverage and test coverage more than 99% ?

I showed you how to fish and now do you want me to spoon-feed you? It is part of a much larger software suite that requires deep pockets you may not have, but useful to know. Not only is DFT important but now fail-safe design. Look closely at the one supported by Infineon, Samsung and NXP.

 

[fragnen]

I showed you how to fish and now do you want me to spoon-feed you? It is part of a much larger software suite that requires deep pockets you may not have, but useful to know.

Is not the industry practice is to insert necessary DFT logic completely only using tool for all the DFT logic required by the design?

 

[D.A.(Tony)Stewart]

There are design specs for failure modes and probabilities of failure and methods to test them such as J-Tag, dual-port bus, and voltage, temp., frequency, as stress factors.

There are many rules that depend on many specs for DFT logic and many different strategies for implementation, test time capabilities, and cost of software depending on complexity and bandwidth. There is no generic solution because each designer has different priorities and specs and many tools to choose from.

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