DFT interview Questions

1. In your design you have dual port memories each working at a different frequency. What is the clock frequency you use for testing (MBIST)?
2. When a failure is detected in parallel testing of memories, how do you know which memory is failing?
3. What are the extra pins needed for BIRA (Built In Repair Analysis) implementation?
4. What could be the possible reasons for scan chain failures during GLS (Gate level Simulation)? Other than setup issues.
5. Did you got any issues during timing simulation of MBIST patterns?
6. What are typical frequencies for scan shift, MBIST tests?
7. How is it different implementing MBIST logic for ROMs, SRAM, DRAMS, and register files? Can same controller handle all these? What are the typical issues faced?
8. What are the differences between IJTAG and JTAG standard?
9. What are the differences between Boundary scan and IEEE1500 standards? Other than Boundary scan is used for board level testing and the IEEE1500 for core based testing.
10. What is the effect of LOS method for testing delay faults on the tester?
11. What are the typical issues you face during timing simulation of scan and MBIST patterns?
12. What are copy and shadow cell? How are they useful?
13. What are the typical clock skew issues you faced during post layout/ timing simulation?
14. How do you implement DFT for a design have lot of Analog blocks? How to improve coverage?
15. How do you test at-speed faults for inter clock domains?
16. Are multi-cycle paths tested in the design?
17. Why do you need multiple-load patterns? What are its advantages over basic scan patterns?
18. What are the typical steps to improve coverage when our coverage target is not achieved?
19. Steps to fix broken scan chain issues during ATPG? Step by step procedure to find the issue?
20. What is sequential depth?
21. How to specify clocks for at-speed testing in encounter test or any other tool? What is the syntax?
22. In SDF we have 3 values best, typical and worst case? Best is for good processor, less temp , high vol and worst is reverse. What is typical?
23. What is split capture?
24. What Is the most challenging issue you faced? How you fixed it?

1- MBIST is frequency independant, I will used the max frequency allow/check by STA.
2- MBIST engine design dependant.
3- ?
4- timing issue, difference of model between verilog used by similutor and ATPG tool.
5- no.
6- see respond 1.
7- ROM need only to read all address, and accumulate in a CRC. For S/D RAM & R, that is IP-provider dependant, whose will indicate the bist engine to apply.
8- IJTAG is to manage multiple JTAG in a SOC.
9- ?
10- ?
11- see 4
12- ?
13- no issue with skew.
14- add feed-back, and need to control the analog input pins from digital core.
15- try to have only one clock domain during scan.
16- no.
17- to improve coverage.
18- analyze which sub-block has a low coverage, generaly add feed-back in scan mode, or test point.
19- check the scan mode is properly enable, the reset is stable state during shift, and the clock is visible by all scan element during the shift.
20-
21- no idea.
22- typical is power estimation.
23- transition fault capture.

Hi rca,

Thanks for taking time to answer my questions.

In functional mode one port of a dual port ram works at 100 MHz and the other port at 125MHz.
What will be your MBIST clock frequency?(Assume the design supports upto 130MHz)
And which is the best way to provide the MBIST clock, Direct from the tester or an internal clock from PLL in this case?

can you please also answer these few questions


What is the maximum operational frequency of the tester you worked on?
What is the maximum MBIST frequency you worked on?
What is the maximum Shift frequency you worked on?


Thanks
Srikanth

I don't expect the pad could follow the 130MHz, no?
so your MBIST engine could work on the internal clock and at the maximum frequency.

My design works at low freq >80MHz, and so the communication between the tester and the chip are up to 20MHz, and the internal program could used the max allow frequency.