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wht is dft?
wht is the diffrence between verification and dft?
difference between defect, fault and failure?
wht is observability and controlability?
wht is scan?
how can we perform scan operation?
wht is serial and parallel loading?
wht is the difference between sequential and combinational atpg?
wht is atpg?
wht is drc violation?
wht is fault model?
how many fault models are there?
wht is scan stiching?
different command option....
wht is bist?
wht is bisa?
wht is bscan?
some other questions can be..
formulas for test data voulme, scan chains in data compression mode..
wht is the difference between the coverage reports from dft dsm and frm ttmax?
In scan chains if some flip flops are +ve edge triggered and remaining flip flops are -ve edge triggered how it behaves?
What you mean by scan chain reordering?
its my request to the senior dft memebers of this forum..plz suggest some more dft questions which can be asked in a interview
Here are few interview questions from my previous interview.. These are more focused on ATPG generation and scan insertion.
How is logic transition fault is different from memory transition fault.
What are RAM sequential patterns?
Diff b/w Named Capture Precedures and Clock Procedures
What are the typical scan clock frequencies?
How much is your design count? Complexity?
What is possible cause of simulation mismatches when you simulae the generated ATPG patterns? what is right way to debug them?
how do you solve coverage issues?
Hi Badola,
Typical scan frequency is the frequency that most of the ATE's use when scaning in the data to the scan flops. it is typically around 1-10 Mhz.
Hope it helps,
~V
some other question:
1. what is normal mode and at-speed mode?
2. what is mbist?
3. what is dft coverage? how to get high dft coverage?
4. normal flow for dft ?
Here are few more with my answers... ( DISCLAIMER NOTICE ... )
(*) Whats the difference between structural and functional vectors.
**broken link removed**
(*) What the major problem faced in dft with tri-state buffers and how is it resolved.
1. The major problem is from the tester end, not all testers are able to measure Z.
2. For the IDDQ vectors, there can be no Z in the design, there is quite a lot of current when a pin is in Z state. A floating bus that is a bus with z on it will drain too much of current and hence loosing the objective of the iddq vectors.
3. Next these tri-state buffers are generally used for sharing the bus, so there has to be a dft logic so there is no contention on these bus during test.
(*) Give three conditions where bus contention can occur.
1. During the shift ( i.e load of the scan chains )
2, During the forcing of the PIs
3. After the capture clock , the flops may capture any thing which may lead to the contentions.
* Which is advantageous, launch at shift or capture launch.
Also a new technique is being used now is to pipe line the scan enable, and negating the scan enable in advance so that by the time of capture is to be done, the scan enable is low.
* P1500 funda!
It is similar to BSDA but at the chip level , instead of the board level. The major difference is that in the BSDA
we are sure that the chips are OK and then do the board testing. But in the case of P1500 , we are not sure of anything, each and every core has to be tested.
* How to achieve high fault coverage. How to increase it.
1. 100% scan design
2. More number of test points
3. No Xs in the design
4. Use sequential patterns
5. Completely defined netlist, i.e there should be no floating outputs, or un connected inputs.
6. There should be logic to certain that there would be no contentions on the bus
7. Avoid floating bus using bus keepers.
* latch - how is it used in dft for sync two clock domains.
Latches are used as lockup latches in the scan chains. These are inserted in the chains where ever there is a change in the clock domain. By clock domain we mean, two clocks or the same clock with phase difference.
Let us have a condition here to explain the things; we have a design with 2 clocks CLK1 and CLK2. There is a single chain in the design, which means that the scan chain have flops which can be clocked by either of the clock.
The tool by default will order the flops in the scan chain such that first we have one clock domain's flop followed by the other domain flops. Let us consider that the CLK2 flops follows CLK1 flops.
Now consider the flop which is at the boundary that is the one where the output of the CLK1's flop is going to the CLK2's scan_in. Clock skew between these successive scan-storage cells must be less than the propagation delay between the scan output of the first storage cell and the scan input of the next storage cell. Otherwise, data slippage may occur. Thus, data that latches into the last flop of CLK1 also latches into the first flop of CLK2. This situation results in an error because the CLK2's flop should latch the CLK1's "old" data rather than its "new" data.
To overcome this issue we add the lock up latch where ever there are clock domain crossing. In our example we would add a lock-up latch which has an active high enable and is being controlled by inverted of CLK1. Thus becomes transparent only when CLKA goes low and effectively adds a half clock of hold time to the output of the last flip-flop of clock domain CLK1.
* Fault types
The different fault types are
1. Stuck at fault model : The node is modeled to be stuck at some value 0 or 1 depending on what we are targeting.
2. Iddq fault model : This is similar to the stuck at fault model but here instead of measuring the voltage we measure the current . In a CMOS design at the quiescent state, ideally there is suppose to no current in the silicon, if there is current then some node has either shorted to ground or to the power.
3. Transition fault model : This is considered to stuck at fault model within a time window. The value of the node changes but not within the time ,at which it should change .For detecting such faults we have two vector for each pattern one for launching the fault and the other to capture the fault. The time between the launch and the capture is supposed to be equal to the time at which the chip would normally function. This is the reason it is all called at-speed test.
4. Path delay fault model : In this fault model ,instead of concentrating on a single gate of the netlist ,we generally are concern with a collection of gates which forms a valid path in the design. These are generally the critical paths of the design. Here again we have two vectors for each pattern. Do let me know if you know what is a valid path ( don't feel offended I am just writing this because you are out of touch with all these technical jargons since long , otherwise I hope you must be knowing them).
The transition faults are also measured at the paths ends, but the major difference between the transition and the path delay is that in the path delay we give the path where as in the case of transition the tool itself selects the path for give fault.
The fault location for IDDQ, stuck-at and transition are same.
5. Bridging fault model : this is a new model which is gaining importance . In this case any two close lying net may effect the value of each other. There is generally a victim and another is a aggressor, so an aggressor forces some value on the victim . We first find the coupling capacitance of each net pair, then depending on the specs we may select some nets which have coupling capacitance more then specified value, these are selected and then these become the fault locations for the ATPG.
* Does the dft vectors test the functionality of the design also?
No the dft vectors does not test the functionality of the design. It can be otherwise that is we can use the functional vector to test fault grade them and use the same for finding the fault coverage using these vectors. The dft vectors are generated keeping the design in test mode , so they won't be beneficial for the functional mode. But note this that there may always be an overlap in the patterns.
* How do u break combinational loops. (*)How does introducing TIEX will eliminate combinational loop. [ I told him by forcing known value we can break the loop]
By adding a tiex gate we can break the combinational loop. First what is a combinational loop. The value is not stabilized, there are oscillation. So if we place a X gate at some place in the loop, we are not propagating the deterministic value which was causing the oscillations.
Adverse Effect : Any X in the design would reduce the coverage.
The second solution would be to place a buffer with unit delay. In this case you would require sequential patterns. Please note that we are not placing any Tiex or buffer with unit delay in the netlist, it is just that we are telling ur ATPG tool to model them for the ATPG purpose. So you won't see any tiex or buf with unit delay gates in the netlist.
* What is scannability checking.
I think this relates to the scan chain integrity. The first pattern that is pattern0 in most of the ATPG tool is called the chain test pattern. This pattern is used to check the integrity of the scan chains, to see if the scan chains are shifting and loading properly; if the scan chains itself have a fault there is no use checking the full chip using this chain.
* Give three Clock drc rules and how to fix them.
1. Clock not controllable from the top. ( Use mux to controll the same)
2. When all the clocks are in off state , the latches should be transparent ( add logic to make them transparent)
3. A clock must not capture data into a level sensitive (LS) port (latch or RAM) if that data may be affected by new captured data. ( for FASTSCAN : clock_off simulation on and for TetraMAX : set atpg -resim_basic_scan_pattern ;-) )
* What does test procedure files have?
The test procedure file contains all the scan information of your test ready netlist.
1. The number of the scan chains
2. The number of scan cells in each scan chain.
3. The shift clocks.
4. The capture clocks
5. Any test setup procedure required before starting the test pattern generation
6. The timing of the different clocks.
7. The time for forcing the Primary input , bidi inputs , scan inputs etc
8. The time to measure the primary outputs, scan outputs , etc ..
9. The pins which have to be held at some state in the different procedure as load_unload, shift etc ..
(*) What problems u faced while inserting test points.
The problems u faces while inserting test points ,
I don't think there is any problem, except
1. Selecting the best candidate location for the test points.
2. Area over head
(*) If enable pin of tri-state is 0, the output is Z. how does tool treat this Z as in DFT. How is Z handled.
It depends on the tester. We can customize the tool to generate the patterns
The cause of the violation was setup, absolutely. If you slow down the frequency you're giving more time to the signals to go through all the logic, so those signals which were failling to reach the setup arrival time requirement now have enough time.
More question:
1. what's the different using sync reset or async reset?
2. what's the affect for the coveray of the two reset?
3. how to do IDDQ below 90nm?
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