Hi All,
I am doing DFT insertion for the first time. Now I am stuck fix a violation " Reset being used as D input to a DFF".
I tried to fix it using autofix option by enabling -fix_data enable.
But during preview_dft it is saying that no violation needs to be autofixed.
Can anyone help me to identify what went wrong.
My script is posted here.
read_verilog -rtl top_mod.v
current_design top_mod
create_port -direction "in" {scan_in1 scan_in2 scan_en TESTMODE} //Create test ports for the design since they dont already existing
create_port -direction "out" {scan_out1 scan_out2}
set test_default_scan_style multiplexed_flip_flop
set_dft_signal -view existing_dft -type ScanClock -port {clk_1 clk_2} -timing {5 10}
set_dft_signal -view existing_dft -type Reset -port rst_a -active_state 1
set_dft_signal -view existing_dft -type Constant -port TESTMODE -active_state 1
//I have a doubt whether TESTMODE can be declared as Constant, as it is used as control signal for autofixing
link
source design.sdc
create_test_protocol
dft_drc
compile_ultra -scan
create_test_protocol
dft_drc
set_dft_signal -view spec -type ScanDataIn -port {scan_in1 scan_in2}
set_dft_signal -view spec -type ScanDataOut -port {scan_out1 scan_out2}
set_dft_signal -view spec -type ScanEnable -port scan_en
set_dft_configuration -fix_reset enable
set_dft_signal -view spec -type TestMode -port TESTMODE
set_dft_signal -view spec -type TestData rst_a -control_signal TESTMODE
set_autofix_configuration -type reset -test_data rst_a -control_signal TESTMODE -fix_data enable
preview_dft
insert_dft
Thanks in advance..