[DFT] IDDQ Testing Fault Coverage

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The IDDQ target is to cover maximum no of states for each logic gate in given design. we no need to observe any fault outside.
Hence is just a toggle profile. due to these reasons the IDDQ coverage is high with lesser patterns.
 

The IDDQ target is to cover maximum no of states for each logic gate in given design. we no need to observe any fault outside.
Hence is just a toggle profile. due to these reasons the IDDQ coverage is high with lesser patterns.

Thanks for Reply.
But I am thinking that We have only 1 observe point. and that is ground or may be Power Supply current.
So is it true that we have only 1 current measure point i.e. Ground/VDD?
Pl correct me if anything wrong.
If only 1 current measuring pont thn we can detect only single fault with the single pattern.
Is it also true or not?
 

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