All,
I am working with DFT Compiler to insert a scan chain to a digital design.
After the scan insertion, the coverage is very small and I have used "report_fault" to find the parts of the design that have lowest coverage.
I am gettgin back:
Error: The CTL mode does not include valid patino.
Presumable a CTL model is written at some point in the flow and it does not have enough/correct information.
1)What commands cause a CTL model to be written?
2)Does anybody have any further information beyond that which the Design Compiler man pages gives me?
Regards
animotion