[DFT] Architecture - seperate Scan and MBIST mode

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maulin sheth

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Hello All,

I have a design who has a single test pin e.g. gpio1.
if gpio1 = 0 thn functional and if gpio1 =1 thn test mode.

Now my design have a MBIST and Scan mode. I want to seperate both modes. like When MBIST is enabled, scan must be disabled.
if Scan is enabled thn MBIST must be disabled.

I do not have any extra pins, So how I can resolve this issue?

Please help me to solve this.

Thanks in advance

Thanks & Regards,
Maulin Sheth
 

do you have a clock pin in your test mode?
or could you describe how much pins you have in your design (analog and digital pins not included the power pins)

- - - Updated - - -

and one design we used the analog pins (4), and when the test mode pins rise, we capture the values on the 4 analog pins which gives up 16 test modes.
 

Thanks rca,
I have a clock pin in test mode.
I want to know that when we are doing scan disable what does it mean?
It means only that we stop the clock to reach to scan ffs?

Thanks in advance.
 

scan disable means for me, the chip is in functional or test modes.
 

ok.
SO can you please help me to resolve this issue ..to disable scan in MBIST mode and to disable MBIST in scan mode. (We have a same clock and reset for functional, scan and MBIST)

Thanks in advance.

-Maulin Sheth
 

first how much pad do you have (excluded power for the moment)?
 

Total 14 pins. But we require 5 Scan Chain. This is one is compulsory.
so 5 scan chain = 10 pins (5 scan-in and 5 scan out), 1 Test mode , 1 Scan Enable. 1 scan clock and 1 reset.
 

We usually used a shift register of 5 bits with the last bit used to lock the test mode, the 5bits are reset asynchronously by test mode pad when=0, clock by a pad which is force as input when test mode is high, as well another pad is used as data in when test mode is high, to shift in the test modes you want (nand tree, output high/low, scan, mbist....).
Or you could load in parallel, I means 4 pads in input connected to the 4 bits of internal test mode registers, which are capture at the rising edge on test mode pad.
During the scan insertion, these test mode bits must be excluded of the scan chains.

The overall picture is to add RTL code to select the different test mode you want to have to test your chip.
 
correct me if i am wrong : rca and maulin

can't we use JK flop to resolve this issue ?
 

Hello Ramesh,
Can you please clarify in more detail?

But I am thinking is that We mostly use only combinational logic for such type of cases, we dont want to add flop as it is sequential circuit and dependent on clock. When we architect Test Access Mechanism (in short Test Mode Seperator), we mostly use combinational logic only.Hope you understand.
 
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